UCC28070 / Limited drain current at load transient with 90VAC

S.Satoshi

Other Parts Discussed in Thread: UCC28070

Hi All,

One problem has been occurred on their test board which use UCC28070. Can you see below and give your advice? I can share their schematic by off line communication, so please email me directly.

sonoki-s@clv.macnica.co.jp

[Situation]

The drain current is limited at load transient from no load to 1.64kW at 90V input. This behavior is not confirmed at 95V input. (See Figure 1)
This can not be resolved to increase RIMO and peak current limit threshold.•This behavior at 90V input can be resolved to change the bottom resistor at VINAC from 11kohm to 12kohm. (See Figure 2)
However the ratio of divider value between VINAC and VSENSE can not be conformed if the bottom resistor at VINAC is changed to resolve it.

[Question]

Please let me know the possible cause of this behavior.
Please consider the solution to resolve this behavior instead of changing the bottom resistor at VINAC

Best Regards,

Sonoki / Japan Disty

over 9 years ago

0 S.Satoshi over 9 years ago

Guru 21675 points

Hi All,

I'm looking forward to your response.

Best Regards,

Sonoki / Japan Disty

0 Peter Meaney over 9 years ago in reply to S.Satoshi

TI__Mastermind 31580 points

Hi Sonoki

We will take a look at this. It will early next week before we will be able to give you a reply.

Regards

Peter

0 S.Satoshi over 9 years ago in reply to Peter Meaney

Guru 21675 points

Hi Peter,

Thank you for your support. I'm waiting for your reply.

Best Regards,

Sonoki

0 S.Satoshi over 9 years ago in reply to S.Satoshi

Guru 21675 points

Hi Peter-san,

Please let us know the concern when the ratio of network on VSENSE and VINAC is not identical if it's not difficult to define the possible cause of this behavior. They could resolve this behavior by using following network.

VSENSE : Rtop=1.44Mohm, Rbottom=11kohm

VINAC : Rtop=1.44Mohm, Rbottom=12kohm

Best Regards,

Sonoki

0 Peter Meaney over 9 years ago in reply to S.Satoshi

TI__Mastermind 31580 points

Hi Sonoki-san

My colleagues in the US suggest that the PKLMT is probably set too close.

A 1.44M + 11K divider puts 90V just under the 1.00V Kvff level threshold to go into level 2, so it stays in level 1.
So the IMO gain is highest and the load step kicks VAO up to the max, driving maximum current which hits the PKLMT.

A 1.44M + 12K divider puts 90V just over the 1.00V Kvff level threshold so it is in level 2, and the Kvff divider is larger.

So the IMO gain is lower and the VAO is still up to the max, but IMO drives less peak current which avoids the PKLMT.

Using the 12K to “solve” this will merely push the problem to a lower input voltage (maybe 87V or something).

They suggest moving PKLMT up by 30% or so to get it out of the way, then run the load step at the lowest expected line voltage, and capture the peak current. Then reset the PKLMT to a suitable margin just above that level.

Regards

Peter

0 S.Satoshi over 9 years ago in reply to Peter Meaney

Guru 21675 points

Hi Peter-san,

Sorry for delayed response. Our customer tried to move PKLMT up but the problem was not fixed.

Then can you confirm the concern if the difference ratio of network on VSENSE and VINAC is used? Now they'll plan to use following value I already informed.

VSENSE : Rtop=1.44Mohm, Rbottom=11kohm

VINAC : Rtop=1.44Mohm, Rbottom=12kohm

Best Regards,

Sonoki

0 Peter Meaney over 9 years ago in reply to S.Satoshi

TI__Mastermind 31580 points

Hi Sonoki-san

Do you know what % increase they made to the PKLMT ?

Regards

Peter

0 S.Satoshi over 9 years ago in reply to Peter Meaney

Guru 21675 points

Hi Peter-san,

They changed RPK1 and RPK2 as below to increase Peak Current Limit.

Before : RPK1=10kohm, RPK2=16kohm
After : RPK1=10kohm, RPK2=24kohm

Best Regards,

Sonoki

0 Peter Meaney over 9 years ago in reply to S.Satoshi

TI__Mastermind 31580 points

Hi Sonoki-san,

I assume RPK1 and RKP2 are in parallel, and that the resistance decreased by about 13%, which should have increased the peak current capability, but the customer did not see any improvement, is that correct?

Regards

Peter

0 S.Satoshi over 9 years ago in reply to Peter Meaney

Guru 21675 points

Hi Peter-san,

They changed resistor value as below and then they did not see any improvement.

And also I'd like to have your comments for concern at different ratio of VSENSE and VINAC divider are used.

Best Regards,

Sonoki

0 Peter Meaney over 9 years ago in reply to S.Satoshi

TI__Mastermind 31580 points

Sonoki-san,

The feedback that I have is that there is little risk in using the VSENSE and VINAC divider that the customer has determined to solve the issue.

I do not understand why the change to the PKLMT did not make any improvement.

Regards

Peter

0 S.Satoshi over 9 years ago in reply to Peter Meaney

Guru 21675 points

Hi Peter-san,

Thank you for your comment. Can you give further comments about little risk? What risk should they consider?

Best Regards,

Sonoki

0 Peter Meaney over 9 years ago in reply to S.Satoshi

TI__Mastermind 31580 points

Hi Sonoki-san,

The customer should measure the THD and Power factor of the PFC stage to determine if there is any negative impact on these values with the mismatch in VINAC and VSENSE resistor divider values.

The probability that they will see any difference in performance in low but it is worth checking.

Regards

Peter

0 S.Satoshi over 9 years ago in reply to Peter Meaney

Guru 21675 points

Hi Peter-san,

Thank you for your comments. I understand that the risk are the possibility of decreasing THD and PFC performance due to the mismatch in VINAC and VSENSE resistor divider values.

Best Regards,

Sonoki

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UCC28070 / Limited drain current at load transient with 90VAC