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No load state of TPS54318

Elvin Joy Serrao
Intellectual 330 points
Other Parts Discussed in Thread: TPS54318

We have used step down SMPS TPS54318 in one of our designs. The SMPS generates 1.2V output from input of 5V. The maximum load current at 1.2V is around 1A. Now we have a requirement where we need to remove all the devices from the board that use 1.2V supply. Thus there will not be any load current drawn from the SMPS. In this case what will be that state of the SMPS? Will be be shut off or the output voltage will still remain at 1.2V?

Note that we cannot remove the SMPS from the board.

Regards,

Elvin

  • 0
    TI__Guru**** 191445 points
    TPS54318 will regulate to the set output voltage of 1.2 V even with no load.
  • 0 in reply to JohnTucker
    Intellectual 330 points
    As per datasheet of TPS54318 (SLVS975B –SEPTEMBER 2009–REVISED DECEMBER 2014) page 12, when the COMP pin voltage is pushed low to the minimum clamp, such as during a load release event, turn-on of the high-side power switch is inhibited.

    In the above case the SMPS output voltage will eventually fall to 0V. Please confirm.

    Regards,
    Elvin
  • 0 in reply to Elvin Joy Serrao
    TI__Genius 11095 points
    Hi Elvin,

    As the datasheet mentions, when the minimum comp clamp is reached, the high-side MOSFET will be inhibited, and the output voltage will fall as a result, however, the control loop will raise the comp voltage back above the clamp to demand more energy into the output when this happens, which will again allow switching.

    This is done for two reasons -
    (1) load release (e.g. 3A to 0A) response. When the output overshoots due to a load release, this causes the comp voltage to undershoot, eventually to the clamp. This prevents the high-side switch from turning on again, leaving the low-side switch on, until the output voltage is back within the expected range. i.e. this reduces the amount of overshoot seen for a given load release.
    (2) monotonic start-up. At the beginning of soft-start, the duty cycle demanded vout/vin is less than the minimum on-time. If the device were not able to skip a pulse (which it does because comp is near this clamp), minimum on time pulses would cause some oscillation during start-up until the output voltage was high enough to meet the min. on time limitation. This is also why we have frequency foldback, to improve start-up monotonicity.