BQ77910A turns off after inrush current pulse.

It sounds like you may be getting a reset at the current protection.  It may be a marginal condition which depends on time or chance and may also depend on the capacitor tolerance or characteristic variation on different boards.

ZEDE bouncing high may be more likely to cause a shortened delay to trip or false trip of some type.  What you describe does sound more like a startup delay as you suspect.  See section 2 of www.ti.com/lit/slua612.  Look for transients on BAT.  Look for capacitor placement on the board, unexpected impedance between the cap and BAT pin, or the currents from the situations described in the app report.  You might also check to see if the capacitor is performing as expected.

The time delay setting for the short circuit condition is 960uSeconds. I assume that means that the short circuit condition must persist for 960uSeconds before the BMU will respond (please confirm).

What I am seeing is that the BMU is entering the shut mode long before the 960uSeconds has passed. Entering the shut down mode has been confirmed by verifying that the 3.3V regulator output is turned off and begins to decay at this time. Below is a list of things I have confirmed;

The transients on VBAT at the time of shut down are far below the spec limit of 1v/uSec.

The transients on ZEDE pin at the time of shut down are not great enough to be considered a logic high. I have also decreased the pull down resistor on ZEDE to 3K with no noticeable impact.

The units that do not have this issue have noticeably less inrush current, around 20% less.

The understanding of the chain of events that cause this issue are as follows;

1. The BMU is turned on by connecting the discharge FET to the discharge gate drive pin.

2. The battery pack begins to charge the bulk capacitance on the system bus. A relatively large inrush current spike occurs.

3. The BMU goes into shut down mode as verified by the 3.3V regulator shutting down. The VBAT and ZEDE pins on the BMU appear to be well behaved.

4. Our circuitry applies the charger reference voltage, which is required to wake up the BMU.

5. Approximately 100milliseconds passes (spec’d wake up time), the BMU wakes up, turns on the discharge FET, the current inrush spike occurs, the BMU shuts down, and 10Hz oscillation begins.

    

   I am considering designing a soft start feature into our next version, but this is not addressing the root cause. I would really like to understand this shutdown mechanism. Any thoughts on what could be causing this, or what tests may be helpful to better understand the issue would be appreciated.

   Thanks,

   Kevin

Yes, if you have 960 us selected the current must persist (voltage on the sense inputs) for that time (with tolerance) before the part trips short circuit protection.  The input is sampled (digital delay) so if you have dropout the time may be extended, but normally the sense input filter will take care of that.

The other pins which come to mind immediately are VSS and VREG.  The part knows VBAT with respect to VSS, also VREG.  Since you see it turn off much faster than the SCD delay it likely is a reset - DSG is likely going off because the part resets rather than the part resetting because DSG went off.

VPOR is based on the VREG voltage, see the spec on datasheet page 8.  Look at the VREG voltage with respect to VSS at the IC.  If the inrush current pulls down the voltage that may be the cause.  It might be hard to tell if the voltage is dropping before it turns off and falls.  Look also at VSS.  Check your layout to see if the capacitor is located close to the VREG pin, if it is far away noise may be coupled onto the pin.  Check how the ground was routed on your board:  The IC and the VREG cap should be at the same potential without a voltage difference between them influenced by the system inrush current.  Check that the VSS pins on the IC are at the same potential.  Current from one VSS pin through the IC and out the other from a voltage difference could be bad for the IC.

The VREG signal (referenced to VSS) does show an initial dip, which corresponds in time with the current inrush. The VREG dips to about 3.0 to 2.9V in about 60uSec, then recovers to 3.3V in about 40uSec. This appears to be caused by a coupling event. The voltage dip on VREG does appear to enter the POR region (spec’d; 2.7 to 3.2V), and this may help explain the unit to unit variation. The VREG connection does cross the power connection which experiences the inrush current. As soon as the VREG recovers to 3.3V, it immediately starts to decrease again, but with a decreased rate of change, as compared to the initial dip. The rate of decrease is 2324V/Sec. Considering we have a 1uf cap on VREG, this corresponds to a discharge current of 2.3mA. Our external load on the VREG should be around 0.1mA. Is there an internal load which could explain the difference of about 2.2mA?  

After about 280 uSec from the beginning of the second dip, the VREG supply then recovers to 3.3V in about 40uSec. If we assume that we did indeed have a POR, does this 280uSec time period to turn on the VREG make sense?

        As far as the grounding, we incorporated a 1oz GND plane for this circuit. The VREG cap is a 1uf ceramic and is located at the pin 19, 20 end of the IC. In hind sight this capacitor should be located much closer to the VREG pin and with a more substantial trace. It seems logical that the primary issue is that the VREG trace also provides power to a low power logic gate, but in doing so it is routed above the trace that sees the current in rush. So it appears that this is the primary cause of the coupling issue.

        So the 2 questions I have are;

1. Is there an internal load on VREG which could explain a load of about 2mA?

2. If we did have a POR, does a 280uSec time period to turn on the VREG make sense?

    

   Thanks,

   Kevin

1. No, with an EVM shutdown I see about 160 uA to hold up VREG.  Things could be different during transient, but I don't see a peak load on VREG during turn off.  The regulator voltage falls rather slowly.  If the transient is forcing pins below ground the behavior could be much different.

2. It might, the board I tried has about a 200 us delay from CHGST edge to the voltage starting to rise.  Then there is the ramp time from initial voltage to final.

You might measure your system current in normal operation.  You might also touch a 1 uF or slightly smaller grounded capacitor to VREG to induce a POR without the current flow to observe the device behavior.  When I induce reset with CHGST held up I don't see a drop in VREG, it rises again at a ramp after the disturbance cap is charged.  You might also try adding capacitance on VREG at the IC as a test, or possibly re-routing the current for test to see how the board reacts.