UCC28700 NO LOAD REGULATION PROBLEM

Bharath,

Here are some comments and notes from my review of your schematic and circuit values.

1. I see that you have multiple outputs, on many different grounds. With PSR, the primary IC will regulate via the aux, so it will regulate whichever output is most heavily loaded. The other outputs may then increase in voltage, esp if they are very lightly loaded, depending on their individual leakage inductances.

2. You mention that leakage inductance is 60 uH, how was this measured? Was it measured at the primary terminals (1-3) with all other windings shorted out? If so, then this will be a measure of all the leakages in parallel with each other, and could indicate much lower value than reality. I also think that 60 uH is actually not that small – it may seem so as a % of Lp, but at 100 kHz with Rcs = 1-ohm, the 0.5LI^2f power in the leakage would be 1.7 W. I would recommend that the leakage inductance should be measured at the primary pins 1-3, and note the value as each secondary is individually shorted, with all other secondaries open-cct. This will indicate the leakage from the primary to each individual secondary, which will be far more informative.

3. In fact, since the ETD34 core is so large for this power level, and the turns are quite low (secondaries seem to all be in the range of 2T – 5T), it will be difficult to construct it with low leakage. I also think the Bpk is very low ~ 142 mT, the core is being hugely under-utilised. The transformer could be made much smaller by allowing Bpk to increase to ~300 mT.

4. For my calculations, I follow the datasheet equations on pages 18-21. Assuming Dmax ~ 50% at min Vin (300 V), the max Nps is 12.6 (eqn 22) – you used 10, so that seems pretty reasonable. The primary reflected voltage will be ~ 277 V (assuming ~0.7 V Vf on D17). This will help to maximise the duty cycle, which will be good for eff. However, the snubber clamp zeners D18/19/22 may be a little tight to this (360 V Zener clamp), with such large leakage inductance, the clamp zeners may be getting quite warm.

5. If the output power is 18 W total, the current limit should be set maybe 20% above this, maybe 22 W. Scaling all the other secondaries to the main 27.0VE output, this would indicate Iocc ~0.815 A. From eqn 23, Rcs should then be ~1.92 ohm. However, you used 1-ohm, indicating Iocc ~ 1.6 A, or ~43 W. Maybe this is necessary due to the characteristic of the fan loads at startup, but it does compromise the design, since would then be designed for 43-W max power capability, meaning the freq and duty cycle at 18 W would be much lower and less optimised.

6. From eqn 25, assuming Fmax of 105 kHz, the required Lp value is calculated as 3.0 mH for Rcs = 1.92-ohm; or Lp = 1.6 mH for Rcs = 1-ohm. Since you use 1.1 mH, the controller will be forced to run at a higher freq, so it will hit it’s Fmax capability sooner than it will reach the 1.6 A Iocc, it will power limit early.

7. Rs1 value looks ok, nominal start level will be ~270 V. It may need to be adjusted due to tolerance of Ivsl(run), if there a min Vin level where startup must be guaranteed.

8. Rlc value depends on the turn-off delay. There is ~50 ns internal to the controller. Not sure how fast the SiC FET turns off. Let’s say about 250 ns total. With present values (1 mH & 1-ohm Rcs), Rlc should be about 6.8 k. With 1k value at present, the peak current will be bigger at higher input voltage, so more power can be taken, Iocc will increase with line, but so will Pmin. With the recommended values of 3 mH & 1.9 ohm Rcs, Rlc would be ~4.7 k.

9. Finally, section 9.2.2.1 (page 18 of datasheet) verifies that the design can meet the Tonmin (actual Tonmin should be >300 ns) and Tdemagmin (should be > 1.1 us) constraints. With 1 mH & 1-ohm Rcs, Tonmin is 305 ns, this is tight to limit. But Tdemagmin is only 0.99 us, too short. This means that the PSR controller will struggle to regulate at min load because the Flyback interval will be too short for the internal circuits to arm and take a valid sample. This could be one of the causes of the issues seen here. With the recommended values of 3 mH & 1.9-ohm Rcs, Tonmin is 434 ns, Tdemagmin is 1.41 us, both ok with plenty margin.

To conclude:

- I think the combination of Lp & Rcs is not quite right for this power level.

- For sure, the Lp & Rcs values will cause VS sampling and regulation issues at light load.

- The ETD34 core seems very big for this power level, and Bpk of 142 mT is not fully utilising the core capability

- The low turns count of the secondaries will make it difficult to minimise leakage inductance.

- Multiple-output PSR designs will have cross-reg drawbacks, unless the load on all outputs is reduced together as much as possible, and there is a reasonable min load on each output when any of the outputs is heavily loaded. But this is due to the transformer construction and leakage inductances, it will also happen with opto feedback – except that opto feedback can be designed to favour one output, then the others will increase or droop depending on the cross-loading.

- There may also be noise and layout issues to resolve, esp if you say that touching the heatsink causes issues. The drain node of the switch should be tracked as short as possible, with minimum possible copper trace area. I.e. Q1,R9/R70 & TR1 pin 3 all need to very close, connected together with a small short trace. This node has very high dv/dt and will radiate, so it's important to minimise the trace area. Similarly, the drain will capacitively couple to the heatsink, so the heatsink should be connected to local GND 0VSMPS node. The ferrite core of TR1 should also be grounded if possible using copper tape or wire that make good contact to the ferrite and then connect to TR1.6

- Finally, the use of the SiC FET may also be significant. I think the UCC28700 should be able to drive that FET at 100 kHz, but the drain turn-off dv/dt may be much faster than with conventional MOSFETs, and this could also be causing noise issues.


I hope this helps, let me know if you need any more information.

Thanks,
Bernard

Bharath,

I see that you have attached many different transformer docs and design spreadsheets.

Which are the correct or most up to date ones to look at? Which have you attached so many?


To comment on your leakage inductance results, they do make sense. If you calculate the parallel equivalent of all of them, the result is 62.7 uH, which tallies with the 60 uH you reported when you first measured leakage inductance with all secondary windings simultaneously shorted.

To illustrate why the leakage is so bad:
- SWG30 = 0.315 mm Cu, so about 0.34 mm OD.
- Primary is 60T, 60 x 0.34 = 20.4 mm. ETD34 bobbin width = 20.9 mm => 1 full layer.
- For the 24Vsmps rail, this is 5T 1xSWG30. 5 x 0.34 = 1.7 mm => only fills 8% of layer width.
- Due to only 8% overlap between prim and 24Vsmps windings, leakage will be very high.

All windings are ideally multi-strand as many as possible, spread across the layer, to maximise area of overlap with primary, to minimise leakage. This is most important for the highest power windings in particular, take care of them first/closest to the primary, then add the less important aux windings.

Note that the very large leakage on the 24Vsmps winding may be impacting the PSR regulation, even with C19 not populated there could be enough parasitic cap to give a significant LC filtering effect - if the waveform has no region of steady slope (i.e. too ringy or too softly rounded) the internal sampler may not get armed, the sample will be missed. it can happen that the IC repeatedly misses samples for several successive cycles, eventually leading to OVP. I would recommend using more starnds for the 24Vsmps rail to decrease its leakage, since it's used for the PSR sensing.

Looking at some other leakages, the 18Vspm leakage is 380 uH, about half of the 24Vsmps rail, because it uses more strands and has slightly less turns. The 15Ve rail is 263 uH, the lowest, since it uses 8 strands for 3T, so total width is 3 x 8 x 0.34 = 8.2 mm. This has the widest width, so has the lowest leakage, but still is only ~40% overlap with the primary.

Looking at your transformer spec, I also do not see any margin tape or triple-insulted wire being used, so how is the safety isolation provided for the isolated outputs?

In your Excel sheets, you have made your own calculation that are different to recommended equations and method provided in the datasheet and in the TI design calculator.

I would recommend to use the calculations that I previously provided, and modify your transformer construction for lower leakage inductance, esp on the winding used for PSR sensing. This should help improve your power supply performance.

I would recommend liaising with a transformer vendor such as Wurth for advice and help to improve your transformer construction and implementation.

Hope this helps.

Thanks,
Bernard