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UC3825B: How to Disable the PWM IC - during Under Voltage and Over Voltage Condition

Arumugam Rajendran90
Prodigy 20 points
Part Number: UC3825B

I have designed Opamp based UVLO/ OVLO Circuitry with 20V Hystersis , which generates 5V Output Signal during undervolatge and Overvolatge, How to use this signal to disable the operation of UC3825B  PWM  IC ?

Thanks,

  • 0
    TI__Genius 9130 points
    Arumugam,

    The best way is probably to interface to the soft-start (SS) pin. This will ensure that when the UV/OV fault circuit releases (i.e. input voltage within required range), you still get a clean startup with soft-start ramp.

    The SS pin needs to be pulled below 0.2 V to hold the IC in shutdown mode, so you will need to interface your circuit to the SS pin via an open-collector NPN or an open-drain N-channel FET. This can be driven with your 0-5 V logic signal from your fault detection circuit. You may need to invert your circuit polarity to account for the polarity inversion of the pull-down on the SS pin.


    I hope this helps answer your question, if so please click the "verify answer" button.

    Thanks,
    Bernard
  • 0 in reply to Bernard Keogh
    Prodigy 20 points
    Thanks Bernard for the quick reply . Is it possible to ensure 0% duty Cycle, ( complete shutdown ) by this technique? Could you please elaborate more?
  • 0 in reply to Arumugam Rajendran90
    TI__Genius 9130 points
    Yes this will ensure zero duty cycle while SS pin is pulled low.