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TPS54202HEVM-716: TPS54202 working voltage and DC/DC buck converter working voltage in general

Part Number: TPS54202HEVM-716
Other Parts Discussed in Thread: TPS54202EVM-716, TPS54202

Hi everybody,

When I look for a DC/DC step down converter solution, I wonder what is the limit input working voltage for a given output voltage.

For exemple, I find interesting the TPS54202, in the datasheet, I can see 4.5V to 28V input voltage, but when I look at the EVM (TPS54202EVM-716), we find 8V-28V input voltage for 5V output voltage.

In DC/DC buck datasheet, it is not clear in general what is the limit input voltage for a given output voltage (something like the "dropout voltage" in LDO).

Some suggestions ?



  • Generally you will need the input voltage to always be higher than the output voltage. The actual amount is very application dependent. As Vin is lowered towards Vout, the duty cycle increases. As it nears 100 %, the high side FET is on most of the time. The first order approximation for the drop out is then Vout = Vin - (Iout * RDSon). You can do a higher order approximation by considering that the output voltage is the time average of the SW waveform. You can include dead time, rise and fall time and low side FET on time in your calculation.

    For TPS54202, the duty cycle can extend beyond 100 %. The high side FET can remain on until the BOOT charge falls below the BOOT UVLO (the BOOT voltage supplies the gate drive for the high side FET). Other devices may have minimum off time or maximum duty cycles specified in their respective datasheets. In thos cases the respective limits will bound the minimum Vin.
  • Thanks for this answer John, your explain is very clear.

    Just another question : how do you explain that the TPS54202 EVM is specified for 8V min input voltage ?

    If I make the first approximation for 5V output with TPS54202, I obtain : Vin = 5 + (2x0.148) = 5.296V.
    I expect that, with first approximation, I can have 5V output with an input voltage as low as 5.3Vcc ?

  • I did not personally design that EVM, but it is not uncommon to have restricted input voltage range. In this particular case, it has to do with the external UVLO set by R4 and R5. The typical start voltage is 6.74 V and the stop voltage is 5.83 V typical. So once the circuit is started ,the input voltage can drop down below 6 V (see the line regulation chart of figure 4). So with tolerances, and those particular UVLO settings, an 8 V input voltage minimum specification seems reasonable. You can modify the EN resistors R4 and R5 to lower the input voltage range.
  • Ok I understand, the ULVO has been externaly fixed on the EVM.

    thanks for the answers.