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LM22680: LM22680 - UVLO not shutting down regulator

user4636520
Prodigy 70 points
Part Number: LM22680

I have been doing brown out testing on my product recently as we have been finding that it is entering an unknown state and not recovering if the input voltage dips too low. I am half wave rectifying 24VAC and feeding the result into the LM22680 to create a 3.3V rail. Upon investigation, it looked like the regulator was not regulating correctly when the input ripple dropped low enough so I added a voltage divider to the enable pin to utilize the UVLO feature of the chip. Before the addition it would start behaving erratically at 6.8VAC, after the addition it had the same problem at the new 15VAC limit I setup. I connected it to a DC power supply and the UVLO works perfectly and cuts out exactly when I would expect it to, but when connected to the ripple of the rectifier it seems to affect it and it droops but doesn't turn off as I would expect. I expect the UVLO to shut off the output when the input voltage drops below the threshold in the spec sheet (~1.6V at the enable pin) and then not turn on again until it rises back up through the hysteresis voltage (+0.6V), but this is not what I'm seeing.

The picture below shows the resulting waveforms with the UVLO circuit connected. The blue trace is the input ripple (2V/div, zero is off the screen), yellow trace is the output from the regulator (1V/div, zero is -3V from center marked by the yellow 1 on the left side). The ripple drops low enough to trip the UVLO, which cause the output voltage to drop from 3.40V to 2.4V for 4.2mS until the rectifier cap is able to start charging again and bring the input voltage to an acceptable level again.

  • 0
    TI__Genius 11085 points
    Does the Vout loaded? If there's no load, output capacitors may take a long time to discharge. Try adding a resistive load at the output and test again.

    -Yang
  • 0 in reply to YangZhang
    Prodigy 70 points
    Shoot... I think you're right. Thanks a lot! Your answer was very helpful.

    For future users of this forum post, here is what I did:
    I started adding a smaller and smaller resistive load (starting at 1k, the 100R, and finally as far as 10R) and the slope of the bottom section started changing. The only explanation for why I have two slopes is that the UVLO trips right when the output starts to fall, the processor and other stuff is on and continues drawing current which is why I have a steep slope initially. When the voltage gets too low the PMIC and processor running off of the 3.3V rail turn off, at which point the demand on the capacitors is low so the slope flattens out until the UVLO lets it turn on again.

    My new issue, which I need to resolve is draining those caps. Currently I'm have to sink several hundred mA into a resistive load, which is not a useable solution on my design. The only thing left for me is to investigate reducing the capacitance.