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TPS5103: Shunt capacitor on current limit resistor?

Part Number: TPS5103


I had designed the TPS5103 into my customer's 400 cycle (ground support) regulator back in 2004. The 5103, used in the HYSTERETIC MODE, drives two power FETs that provide about 7 amps DC (variable) of PWM excitation to the 400 Hz generator's field winding. The design was prototyped OK, committed to printed boards and production units manufactured in 2005. About 100 of these have been in service for 10 years with the only trouble being that sometimes the 12 VOLT DC support power would surge and damage the 5103.

Recently we decided to redesign the board incorporating surge suppression/regulation for the support power while leaving the TPS5103 circuit basically the same. When testing the redesigned boards we found there is extreme sensitivity at pin 15, the over-current trip pin. Even 20 pf loading (two scope probes) would usually snub oscillations there. With reference to the TPS5103 data booklet SLVS240A (May 2001) EVM schematic on page 20, a capacitor, C11, is shown shunting pin 15. Note that on page 31 B/M C11 (Open) is footnoted as "for optional mode test only" and nothing else can be found in the publication on this issue. Continuing to experience oscillations I TEMPORALLY  tacked in 220 pf on the prototypes and moved on. Later I see another TI customer had designed in a 10 nF capacitor there in their 5103 application (unrelated to ours). We still have some oscillation issues on the output high to low transition.

From time  to time I find a "latch off" mode where the 5103 shuts off after a few seconds of high output current in a circuit similar to the EVM schematic. It latches off until the supply power is interrupted NOT until the load is removed as stated in the 5103 data. Is there an enable latch of some sort internally? I will test this further. Along a similar subject, we previously noticed that the  STBY pin 10 logic function is not consistantly defined in the 5103 data booklet. We just tied it to a 5 volt regulated source available in our product. Is this acceptable?

Finally, how is the Ct capacitor at pin 4 defined for the HYSTERETIC MODE application?

I would really appreciate help with the 5103 as we have been de-bugging this redesign for over a month now and are unable to resolve these issues.

Best Regards,

David Kent, Design Engineer,

A C Systems,

11953 Springview Dr., La Mirada CA, 90638

  • Hello Kent,

    1, I think over current tip pin has no directly effect on the output oscillation issue. Could you upload the oscillation,SW waveform and the P15 wavefrom.

    2, Could you introduce the "latch off" mode in deatil or upload some waveform and what's the test condition?

    3, If you don't use stanby mode, you can tie Pin10 to a 5 volt regulated source.

    4,The hysteretic mode is selected by connecting the Rt pin to 5 volt. Please don't care CT.

    best regards.