Hi,
My customer sets the switching frequency setting to 700 MHz.
The waveform of the PWM pin far exceeds the set frequency.
What kind of cause can be considered?
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Hi,
My customer sets the switching frequency setting to 700 MHz.
The waveform of the PWM pin far exceeds the set frequency.
What kind of cause can be considered?
Hi Kenji,
Looking at the switching frequency from the triggered pulse to the next one on the right, shows it to be pretty close to the 700kHz set by the customer. What you're seeing in your persistence capture of phase looks to be period jitter. D-CAP+ does have a bit more jitter than clocked architectures but this may be a bit excessive.
Can you share a schematic or the compensation please? I'd be happy to take a look and give any feedback on reducing the jitter.
Thanks,
Carmen