UCC3837

Hello Robert,

1)   Theoretically any combination of Rcomp and Ccomp that gives the correct frequency domain zero calculation will work - and in this case the frequency domain zero and the frequency domain pole should be approximately the same.  Use x5r or x7r ceramic capacitors ( minimum of 220pF).  Use what is convenient.  As long as the poles and zeros are calculated correctly the relative component values will not affect the circuit.

2) From my reading,  "2mA " is the on-state supply current.  The supply current should be much reduced if either the CAP pin is shorted and or the COMP  pin is shorted (or both?).  Using a FET to turn off Vdd will not damage the device and should reduce the off state current draw to near zero.

3) By "low leakage" it means that the leakage current through the FET should be several orders less current than the charge pump current (10uA). 

4) I will look into this further.  The output is limited to three times Vdd - and Vdd is limited by the 5V clamp at the input to the charge pump.  But due to inaccuracies in the circuit the actual maximum is 16.5V.

5) Feed forward caps often help stability, extend the bandwidth of the control loop, and can be used to program soft start.  Whenever I am optimizing the loop I experiment with the feed forward cap to see if it improves the transient response. 

Bill

Hi Bill,

Thank you for the reply. Basically I am a digital engineer and have learned about LDO controllers over the years to support my products (www.Smart-Fly.com).  I will probably turn Vdd off to shut the unit down.  For #5, how do I experiment with the the feed-forward cap.  I have not had to do this before. Thanks again.

Hi Bill,

Here is my current schematic, I need to remove the gate pulldown.  The values are not calculated yet.  Parameters are

Vin = 6.0-8.5V

Vout = 5.2-6.5V (adjustable)

Current = 7.5A continuous, 15A peaks, 15A-20A over current limit

Any suggestions on where to start with the feed-forward capacitor?

If you want to see what I do look at   www.Smart-Fly.com

Thanks,

Hi,

I updated the schematic and finished the PCB.  I have attached them.  I am not sure if I did the gate capacitance calculation right.  The gate Cgs is 14nC.  The Vgs is 2.5V.  I calculated a gate capacitance of 5600pF for these values.  Thanks,

PCB PDF.

Robert,

Cool products.  I would start with a feed forward capacitor of say 1nF.  I wish that I was designing this linear controller in parallel with your design.  Good luck.

Bill

Hi Bill,

Yes, LDO controllers are getting harder and harder to find.  I wish you guys would update yours.  This is nice but I'd like a smaller package.  Does 5600pF sound right for the gate capacitance?  I went by data sheet and I think I gave you the parameters in the other e-mail.  Also read about how Rcomp and Ccomp changes affect load response so I understand that better.  I should get the PCB out by the end of tomorrow.  On transient response, I have a programmable load, what would you suggest to check the response.  I was thinking about 50-100ms high load and then 50-100ms light load.  Thanks for taking the time to help me understand this part better.

The effective gate capacitance is the gate charge divided by the gate voltage.  This gives the correct units for capacitance (Coulombs/Volt).  You correctly calculated the gate capacitance 14nC/2.5V = 5600pF.

Hi Bill,

I have one last question.  An FAE at another company told me I could tie the comp outputs together to force current sharing (I know it will not be perfect).  In this hobby, with planes costing up to $25,000, the pilots want redundancy.  I have attached a schematic where I use two of your units and have over-voltage protection (I forgot to connect the two FB pins together).  Do you think this will work and share current to 20% or better?  I normally expect a FET to fail first but if one of your chips failed, assuming the comp pin basically turned into an open, how would the double compensation network affect the remaining chip?  I plan to prototype this soon, just after I verify my first prototype board.

Robert,

I haven't tried this myself but it sure seems like it would work.  Yes, you can tie the feedback pins together (as you said) using a single feedback network and you can tie the compensation pins together also using a single compensation network.  I am not sure that you will share current to within 20% as this is often difficult even with  current mode switching controllers that are designed for the purpose of sharing current. 

Good Luck

Bill

Robert,

A few more comments:

- Assuming that you  want to share current between the two parallel regulators, the usual way to accomplish this is to use ballast resistors at the output of each regulator.  You will find an attached app note/spread sheet that might help towards this design effort.  Connecting the comp and fb pins will of course improve the current sharing in any case.

- When redudancy is necessary but not current sharing, diodes are typically used at the output of each regulator to provide an "ORing" type function.  Current sharing is not possible using this scheme as one regulator is always biased off.  The benefit of this scheme is that if one regulator fails then it is easy to detect its failed output.

bill

0285.slva250 LDO ballast resistor.pdf

8233.Load Share Ballast and tolerance b.xls

Hi Bill,

I have used ballast resistors before, it works OK but as the tech note says its not great.  I was also shown another way that mimics the balance resistor method for LDO controllers but does not require the high-wattage resistors.  I have attached a schematic.  The PNPs in this case bias the FB just a bit as the load increases.  Kind of neat.  I am looking for sharing as well as redundancy.  If I can get decent sharing each FET will run a bit cooler.  Thanks for all your help here.  Still fighting with sales a bit.  They list the reel price on the site as $1.95 but now they tell me this is the price for 25,000 parts!  Let  me know if you ever get the OK to design a new part.

Hey Robert,

Thanks for the PNP bias circuit - I'll put it in my notebook.

Robert,

I am adding this schematic to this communication chain for completeness - in case another engineer is trying to figure out how to do the same thing.  I am sure that you have had the same idea.  The schematic provides yet another way to force the two parallel linear regulators to share current.

0741.Current Share -TPS7A45xx ds Fig 31.doc

Regards

Bill

Hi Bill,

Thank you for this.  I have seen something similar.  Since I am mostly digital and do not do Spice much, do you have any idea what happens if one regulator fails?

Robert,

Yea, great question!  In your case it wouldn't be so great.  On second look this would not exactly gracefully degrade.

Hi Bill,

If you come across any other circuits that would work more gracefully in case of failure let me know.  ST makes a circuit that I have used on some prototypes that I may employ also that works well, wish TI made something like this.  They are about $1 each, L6615.  National makes something cheaper but it does not work well with high-side sensing which I need, LM5080.

Hi,

This project got put off quite a while but I am now trying to finish it.  I have everything working great except disabling the unit.  I was told that shutting off the Vcc would disable the unit but this does not seem to work.  When I turn off Vcc it still seems to get power, maybe though the CS pin?  Anyway, I need the lowest current possible for this device in the off condition.  The 2.0mA of the unit is too much.  I would appreciate any input you can give me to shut this device down and only draw a few uA of current. I have attached the schematic of the device.

Also, I just tried to disconnect ground as I think I was also told should work and that does not work either.

Per your schematic, it looks like the only place the current could go would be the CS pin.  That then creates a problem because if you don't apply a voltage to VDD but you do apply a voltage to CS, you violate the abs max of the IC.  You probably have currents flowing into CS and out of the other pins.  If you troubleshoot the circuit and measure voltages and currents, I think you will be able to track down the exact leakage path.  I think you are going to need to put a FET in the path that blocks all current from flowing to any pins of the TPS3839.  You could also add a FET to the input of the CS pin.  The input current is very small, so there should not be any appreciable voltage drop across the FET. 

Thanks.  I prototyped using a FET on both Vcc and CS and got mixed results.  Part of this may be the PCB is really hacked up now.  I have sent out for new PCBs that have FETs on both Vcc and CS.  I am hoping that works.  This part is ridiculously resilient.  I even disconnect Gnd with Vcc and CS connected and it worked perfectly.

I wish you guys would make an updated part like this that had an on/off.  This part has a a lot of features that are great for high current LDO applications if it only had an easy way to turn it off.  

Thanks,

Let us know if the two FETs are able to isolate all your current paths.

Hi,

I will.  I am a little worried about the FB pin.  Have you guys looked at doing any kind of new LDO controller?  I know Micrel is selling tons of MIC515xs and Seiko sells a lot of their S-816 Series.  I may have to go back to the Micrel MIC5158 if I cannot get this to work.  Its expensive, larger, requires more caps and is more expensive but works.  Thanks

We do not have any controllers in work.  Can you share you application, volumes, and production date?

Hi,

My volume would not warrant you guys working on a new product.  I only use about 2500 units a year for high-current regulators for rather expensive radio controlled airplanes ($3,000-$25,000 per plane).  I need linear regulators so I do not interfere with the radio reception and because of price.  I need regulators that can handle 8-10 amp continuous with 35-50 amp peaks.  You can see my product line at www.Smart-Fly.com.   I expect to be doing this for long time and I could use a good controller any time it comes available.  Thanks for the interest.

Very cool products.  Unfortunately we don't have anything on the roadmap that will meet your needs.  I hoping the solution to add discrete FETs to break the leakage path works.

OK, thanks for your time Michael.

Hi Michael,

The dual FETs did not solve the problem.  When I turn off the switch the voltage drops from 6.0V to about 4.15V and stays there.  Interesting thing is that if I use a DMM to measure the gate voltage, it starts to drop when the probes are on the gate and will then turn the regulator off.  For what ever reason, the drive on the gate is miniscule but enough to keep the FET on.  I measured the voltage on the Vcc and CS pins and it was down around .012V-.014V so I know it was off.  Seems the gate driver is very, very high impedance when Vcc and CS are removed.  This really sucks for me.  I have a reel worth $2500 that I cannot use now.  Thanks for your help.