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TLV62585EVM-824: TLV62585EVM-824 Gerber

Ben Huang1
Intellectual 655 points
Part Number: TLV62585EVM-824
Other Parts Discussed in Thread: TLV62585

Hi

 

Document No. SLVUB03
TLV62585EVM-824 Evaluation Module

 

As mentioned in the section “Board Layout”:

The Gerbers are available on The EVM product page: TLV62585EVM-824.

 

But I cannot find the gerber file in the link, could you please provide directly?

 

 

Thanks

Regards

Ben

  • 0
    TI__Expert 3465 points

    Hello Ben,

    thank you for your inquire. We will provide soon the Gerbers on the EVM's product page. In the meantime you could start a project in Webench from the TLV62585 product page:

    by clicking on the export button you will be able to get the project files of the PCB used for the thermal simulation:

    with this tool you can also evaluate the efficiency, modify the BOM, schematic and do electrical and thermal simulations.

  • 0 in reply to Emmanuel Granatello
    Intellectual 655 points
    Sir


    Thanks for efficient reply and indication to export PCB profile.
    But there is apparent difference at the glance between the exported PCB and shown as SLVUB03

    May I check the performance of TLV62585 with the exported one?

    Regards
    Ben
  • 0 in reply to Ben Huang1
    TI__Expert 3465 points

    Hi Ben,

    May look different from the EVM, but the functionality and the reliability is the same. Hence, of course you can evaluate the performances of the TLV62585.

    By the way, if your purpose is to only evaluate the TLV62585 alone, I may suggest you to order our TLV62585EVM-824. In this way you will be able start your evaluation in shorter time.

  • 0 in reply to Emmanuel Granatello
    Intellectual 655 points
    Sir

    There is intentional ground pouring from the exported PCB file
    What is the purpose for?

    (1) Mid layer 1 : Shielding area is only occupied beneath the inductor and kept clearance from other pouring in the same layer
    (2) Mid layer 2 and bottom layer : Shielding for the whole plane but “break” at the following positions, such as I/O power and I/O cap

    Should I follow the intention in my future board layout?


    Thanks for reply and recommendation
    Regards
    Ben
  • 0 in reply to Ben Huang1
    TI__Expert 3465 points

    Hello Ben,

    Thank you for asking those clarifications:

    -The grounding on Mid layer 1 is the main ground connection, plus it shields the electromagnetic field create by the un-shielded inductor. The clearance is created to increase the resistance between the inductor's shield and the ground, in order to minimize the injected currents caused by the inductor's electromagnetic field itself.

    -The ground planes on mid layer 2 and bottom layer are there as further shield and to decrease the resistance of the main ground connection paths. Since PCB layer's number is always even, we have two ground planes, but one should be sufficient. Furthermore, Vout and Vin pins are made with through-hole headers. The caps have vias trough the PCB to dissipate heat. Eventually, to accomplish these purposes, "breaks" for IO power are needed to just avoid them to be connected to the ground planes.

    To conclude, your final layout will depend on the whole board, on the layers quantity and if you need the through-hole headers. Anyway I would still use at least one ground plane, the cap's vias for heat dissipation and the shielding technique for the inductor.

    Enjoy your design!

  • 0 in reply to Emmanuel Granatello
    Intellectual 655 points

    Sir

    Thanks for patience and detailed description!

    Fortunately, TLV62585EVM-824 Evaluation Module is now available.

    I am trying to make a correlation with the datasheet and measure the output voltage ripple only (remove the probe hook and long wire clip for GND connection, probing across output capacitor with “short contact” instead)

    Fig 13. PSM operation can be reproduced but not Fig. 15 PWM operation

    VIN = 5V, VOUT = 1.8V, W/O feed forward capacitor, IOUT = 3A

     VOUTP-P (ripple) = 32mV (extremely abnormal ?)

    May I miss something required to pay attention to and take into account?

    Regards

    Ben

  • 0 in reply to Ben Huang1
    TI__Expert 3465 points
    Hello Ben,

    I think you are comparing the EVM performance with the datasheet waveforms. The datasheet waveforms could have been measured with a different BOM, which is it's not specified in the datasheet.

    Anyway, here is a useful tips short video on the subject:
    training.ti.com/measuring-vout-ripple-dcdc-converters

    Go through it and in the meantime I'll get some ripple measurements and come back to you with a more complete answer.
  • 0 in reply to Emmanuel Granatello
    Intellectual 655 points
    Sir

    I have never met such nice guy as you on TI E2E, and very very appreciate for your great support!

    What I do is set a standalone benchmark so the EVM’s performance is required but I have nothing to compare with. Comparing to datasheet is reasonable but found difference

    The waveform attached was measured by the same approach as video shown, and limit the BW to 20MHz.


    Looking forward to the further information from you!

    Regards
    Ben
  • 0 in reply to Ben Huang1
    TI__Expert 3465 points

    Hello Ben,

    Thanks you!

    I have measured the following waveforms by only changing the output capacitor to 47 uF.

    which is very close to the datasheet's performances.