TPS24710: Timing chart for behavior of EN pin

Kato,

Case 1 is the same as figure 2 in the DS. Case 2 has not been characterized as turn on delay isn't normally a design concern and is much smaller as normal power up Vgate rise. It will be in the same general range as for Enable power up as with the Vcc POR shown in case 2. Best for you to check out on an EVM and use a +/- 50% window for tolerance to account for IC-IC and temp differences. Keep in mind that figure 1 and figure 3 also account for Vgate capacitance impact on pulling the gate low when you look at its timing. Pull down on figure 3 (fast trip) is very strong (1A) so Crss has only a small impact. Figure 2 looks at the sourcing current (I-gate) turn on timing. Vgate will lag this.

Brian

Kato,

De glitch is a period of time where the internal circuit ignores the input.  This prevents nusiance triggering that you would not want to happen in a transient environment.

Brian