802.3bt - Current Inbalance between pairs.

Hi Andrew,

The PSE device has current limit for each channel/pair set. If the current exceed this limit, the PSE will shutdown the channel. Our PSE has both 4 pair policing and 2 pair policing, so you don't need worry about the situation you described above. The PSE device will take care of the over current itself. Thanks.

Best regards,

Penny

Hi Andrew,

Yes. Each 4 pair port requires 2 PSE channels/MOSFETs to support high power. 4 pair power delivery is required for >30W applications. Thanks.

An example of 4 pair single signature system is shown below:

Best regards,

Penny

The current flowing on pairs 12 and 45 does not flow tthrough the PSE, it is only the current that is flowing through the other two pairs.  You coudl have the situation where one of the pairs that is connected to _+54V is attached is carrying all the currnet.

How do you protect against this?

Please see the flow. Red one is the current though pair 12, 36; Blue one is the current though pair 45, 78.

They all flow though PSE channel FETs.

Consider this situation.  Where pair 4/5 is broken  there is no FET in the path for the 4/5 cable.  The current that should have flown through pair 4/5 will find its way through pair 1/2.   If pairs 7/8 or 3/6 break the overcurrent situation can  be detected, and controlled. there is both current sence and a Fet in on those pairs.

Of coure the recetifiers will still conduct,   The voltage is still there, and all the current can flow.  There is no 'reverse' path situation.

One can not rely on data 'will not work' either. 

This is a really important question that needs to be resolved and this answer is not really helping me.

Hi Andrew,

This is a known condition in the industry and even applies to 2 pair (if one of the twisted pairs is broken). There is nothing in the current IEEE standard (or the new .bt standard) that will give guidance on this; as such, this should be approached at a system level circuit and not a IC chip level (the IC focuses mostly on implementing the standard).

Most system level designs I've seen do not account for this fault condition. However, I can see how this can be important for an extra level of safety.

In my opinion, I believe Jack's answer regarding the half FET-diode bridge (like shown in the TPS2372-3EVM-757) is a low cost solution and will work well since a high side break will effectively turn OFF the low side FET and allow only two of the pairs to power the load. If the load is operating at max PD load, then the PSE can certainly see this as a fault.

Also his comment regarding the data link disconnecting also might be a good indicator on if the wire is broken (if all four pairs are being used for data).

If more exact current measurements are required, a current sense resistor with an amplifier can be used to detect a specific current level on each of the pairs of the cable. It can be powered from the VDD-RTN side of the PD (after detection and class) or from the bias voltage of your converter.

On the PD side, these over current signal can be used to pull DET low (turning off the internal pass FET), then PSE removes power and recycle until the cable is replaced. Figure 10 in the below app note shows an example of how this PD disable would look like.

HI Darwin, thanks for your reply. 

With 2 pair, the situation is a bit different,  you only have 1 pair  each way.      You can be confident that the currnet flowing 'out' to the PD, must all return on another single pair,   Thus monitoring current in one pair is sufficent.   With the 4 pair, you cna't make that assumption.

One way to protect this, is to to fuse the pair thats not going via the FET,  ( in the example above, that is the side attached to +54V ).   That is probably a wise idea, but fuses are a last gap control if everythign goes wrong to stop a fire.

With the 4 pair, we will of course not bring up power if the cable is broken, at startup as this would fail signature detection.   The fault Is what happens if the cable is damaged while it is plugged in.    

What is the consequnce of having potentially 1.8A of power flowing on (worse case) a single conductor?   If we fused the pairs to say 1A, the worst case would be 0.9A on one conductor.    There will be some increased heating of the cable.    If its a 100M circuit, you may not detect a data loss, ( depending on what pair breaks ). 

Coudl you please expand a bit on what Jack said, because i still can't see how it helps. I'll  have another look.

Somethign I had considered was putting some active current limiting on the +V side, that woudl kick in before the fuse.   The fuse is somethign you cant NOT do, as it needs to be there for regulatory reaons as much as functional..   Obbviously this costs you a bit of energy, and a .7V drop across Q1.   This coudl be compenstated for by increasing the +V side a little.

Maybe i'm makign this problme more complicated than than it needs to be.

Hi Andrew,

Sorry last time we talked, we discussed PDs so I was thinking design on the PD side. If designing a PSE, you're right, you have no control of what the PD bridge will be.

Unfortunately, TI does not have an equivalent FET bridge to the FDMQ8205 part.

For the .bt PSE part, I believe you are already in contact with Penny our PSE apps engineer. She will be able to update you offline with some exciting news. Thanks!