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BQ24630: Problem with the Vref output being out of spec, 4.076V instead of 3V3.

Ivor Kruger15
Prodigy 160 points
Part Number: BQ24630

Hi,

I have a design mostly based on the reference design for a 3S LiFePO4 battery.

I apply 24V to the BQ (checked it on ACN/ACP and on VCC. Draws about 30mA on complete board, so not major fault but the charging does not function.

On closer inspection I measure that Vref is 4.076V instead of the 3V3 specified in the datasheet.

Any ideas why this would be the case?

Other measurements to be done to help resolve?

Schematic below/attached.

Thanks in advance

Ivor

  • 0
    TI__Mastermind 20300 points
    If VREF is out of regulation, then most likely the IC has been damaged.
    Recommend to add another 1k resistor at the your Q3 gate. Please refer to the EVM schematic for reference.
  • 0 in reply to Jing Zou
    Prodigy 160 points
    Jing, thanks for the VERY quick response.

    I followed the circuit as in the datasheet. I see that the supply to the VCC pin is slightly different. What is the purpose of D9 in the EVM circuit (and also thus the extra 1k resistor)?

    Do you have any idea why the BQ would be damaged? Q2 and Q3 protects it from reverse as well as over voltage.

    Thanks
  • 0 in reply to Ivor Kruger15
    TI__Mastermind 20300 points
    D9 is optional. The additional 1k is used to slow down on Q3 to prevent inrush overshoot.
    Just from the schematic, it is hard to tell why the IC is damaged. You will need to submit the IC for FA so that it can identify which pin has been stressed.
  • 0 in reply to Jing Zou
    Prodigy 160 points
    Jing, I just replaced the part and the result is exactly the same. 4.09V on Vref.

    This is the case with a 24V input only, no battery connected this time.

    Sending a chip from South Africa to get a answer like that would be a waste of time and money. Let me rather look further into it.

    Any other ideas?
  • 0 in reply to Ivor Kruger15
    TI__Mastermind 20300 points
    Have you capture the waveform this time when 24V is applied?
    VREF is the output of an LDO, so most likely the input is been over stressed. Can you try again and and probe VCC and VREF?
    Is there any other load connect at VREF?
  • 0 in reply to Jing Zou
    Prodigy 160 points

    I will captured the waveform of VRef and  it is shown below the schematic. Vref is only used at the BQ to generate the setting values for ISET1/2, ACSET and the TS pin. Now where else it is used. The VCC signal rises very sharply to 24V and remains there. I did not save that waveform.

    In the mean time I did find an error. See the redblock in the schematic below. The junction is missing, so two pins  (R41 and R43) was not connected to GND. I have fixed that, but of course the reference is still wrong, so I will replace the chip again now that this error is fixed.

  • 0 in reply to Ivor Kruger15
    Prodigy 160 points

    New chip again after fixing the error for R41 andR43.

    Exactly the same results, event the waveform on VRef looks the same.

    Very confused now.

    I scoped the VCC pin again at 10us timebase and there is no overshoot, very nice damped rise to 24V.

    Another scope trace of VRef with 1us timebase

  • 0 in reply to Ivor Kruger15
    TI__Mastermind 20300 points
    What is the bandwidth setting on your scope?Please use full bandwidth setting.
    VREF oscillates in your scope capture from 3V to 3.8V. Is the IC switchin? Can you plot VCC and VREF at the same scope capture?

    ISET1 and ACSET pin should not cause the issue as ACSET and ISET1 has internal clamp.
  • 0 in reply to Jing Zou
    Prodigy 160 points

    Jing, thanks for sticking with me to try and solve this problem.

    As far as I can tell, the chip is not switching, i.e. no waveform on the inductor. Is that what you meant by switching? The Vref supply is an LDO,right? not a dcdc?

    I also thought that ISET1 and ACSET should not have an effect, but not knowing the insides of the little black box, I thought I would just go ahead and replace it to rule that out as well.

    I have thoroughly checked the VRef pin/trace for possible shorts to other nets but found none. The oscillation present on VRef does not seem to be present on any other pin of the device.

    There seems to be about a 32ms delay from when 24V is applied (VCC) to when ACN/P is starting to rise. The signal on ACN/P is a good looking soft start curve to 24V.

    Below are three plots of the Vref and VCC at 3 different sec/div values. The trigger is setup on VRef. Full bandwidth is used (it is a 2GS/s (200MHz) Tektronix). The oscillations on VRef are at 2.38MHz.

  • 0 in reply to Ivor Kruger15
    Prodigy 160 points
    I have now removed the resistors R35, R36, R37 and R40 from the PCB and checked their values to be correct. No problem there.

    Thus, the only component left on the VRef pin is C33. The results are unfortunately still the same, with the slight difference that Vref spikes a little higher initially, but then settles for the normal oscillation as before.
  • 0 in reply to Ivor Kruger15
    TI__Mastermind 20300 points
    From your scope capture, the oscillation on VREF is ~2MHz. The bq24630 swtiching frequency is 300kHz. Thus the bq24630 cannot generate 2MHz oscillation. Plus, you have confirmed the converter is not switching at all. Since there is no other load connected at VREF, then the problem leads to be ground connection. Please double check your ground and make sure they are properly connected.
  • 0 in reply to Jing Zou
    Prodigy 160 points

    Jing, the PCB is a 4 layer board with ground and power internal layers. Below is snapshots of the area around the chip. The red arrow points to pin 17 for ground connection. It has via directly to ground plane right at the pin. The other picture is of the ground plane.

    As you can see, the middle pad is also connected to ground with multiple vias.

    I also just double checked pin 17 under microscope and it is soldered well. I cannot check the power pad, but it "should " be soldered ok after the reflow.

    I also checked to make sure that the ground is not isolated by any means ( like a island in plane etc).

  • 0 in reply to Ivor Kruger15
    Prodigy 160 points

    Anybody else have any ideas?

  • 0 in reply to Ivor Kruger15
    TI__Mastermind 20300 points
    Hello Ivor,
    Where do you place C33? The VREF is simply a LDO, so either the problem is on the input side or the output side. The input from your scope capture looks pretty stable. Thus we need to take a close look at the output. From the layout capture, we cannot tell where is C33 (VREF cap) placed at. Would you prefer take this off line so that you can share more detailed layout file?
  • 0 in reply to Ivor Kruger15
    TI__Mastermind 20300 points
    How do you measure the VREF voltage? In other words, where is your ground reference when you capture the waveform. Did you use the GND of C33? Or pin 17? or somewhere else? Can you directly probe the voltage across C33?
  • 0 in reply to Jing Zou
    Prodigy 160 points

    The GND I used was a little further away than I would have like, but now I measured it just over the cap. Below are the traces at different sec/div resolution. You will notice it is almost as if the chip is trying to regulate at 3V3 for 3ms but then gives up and goes ballistic.

    Hope this can give you some new ideas. Can we skype chat about it, its a little more interactive and then we don't clutter the forum with all the screenshots.

  • 0 in reply to Ivor Kruger15
    TI__Mastermind 20300 points
    Discussion moved off line. Customer added 100nF cap which solves the problem.