WEBENCH® Tools/LMR16030: Output ripple - PCB design

Hi Brani

My appologies for the late reply, was on leave.

Please find attached screenshots of the ripple (+/- 1V)

I have not as yet tried your suggestions - will do it shortly and send screenshots of the ripple accordingly

Thank you very much for all the help thus far!

HPM-100 Riplle analysis.pdf

Hello Stanley,
There is indeed a large amount of ripple.
It also appears to be very random and wide band.
I think adding small filtering capacitors as close as possible should help.
Please let me any updates.
Regards
Brani

Hello,
since there is no activity on this thread i will go ahead and close it.
Please feel free to re-open if needed.
Regards
Brani

HPM-100 REV 3 Riplle analysis.pdf5265.HPM-100 Schematic.pdfMM173401-3 (HPM-100).zipHi Brani

I have made another pcb - trying my best to follow the suggested layout in the datasheet and other app notes.

The noise seems a lot better (308mV), I do however feel that it is still way to much ripple.

Please look at the layout and waveforms and comment accordingly

I would like to give the layout a last go to see if I can improve - (should I consider a multi-layer with two internal GND planes)?

Hello Stanley,

As first step i would suggest getting an EVM for this device and test its performance in your application.

This layout looks improved, here are my comments:

1. Use 4 layer board if that option is available. Place solid uninterrupted ground plane on inner layer 1. Inner layer 2 can be used for signal routing.
2. Increase input capacitor C1 value to 10uF
3. Switch places between C1 and C13. HF bypass capacitor C13 needs to be placed as close as physically possible to the IC. Currently C1 looks much closer to the IC1 than C13.
4. All components used for IC1 should use "direct connect' to ground plane. You are currently using "relief connect" and that is not optimum for switch mode power supply.
5. place vias on ground side of input and output capacitors and freewheeling diode. 
6. feedback signal return is taken directly form the output side of the inductor L1. This signal should be taken from the point after output capacitor filtering has been completed. This way you will be routing clean signal back into feedback node
7. R5 placement is not as critical, and it could be moved slightly farther away fro IC to open space for placing C13.
8. Increase amount of output capacitance. Replace C12 with 47uF/10V aluminum capacitor (if possible). A single 100nF bypass capacitor (C15) on output should suffice
9. Place HF bypass capacitor between VH1/VH2/VH3 and ground. This will help with reducing high frequency noise on each of these rails. There are currently no bypass capacitors on these rails.

Regards

Brani

6740.LMR16030SDDAR 6V 3A.pdfHi Brani

Thank you so much for the suggestions - I'll start implement it asap.

Can I send you the gerber files to check before I get the pcb made?

Also - just as a matter of interest - I copied the design from WEBENCH (please see attached). 

Hi Brani

Trust you are well.

Can you please have a look at my final attempt to improve the layout and comment accordingly?

Thank you in advanceHPM-100 rev 4.pdfMM173401-4(HPM-100).zip

Hello Stanley,
This layout looks improved.
Just a couple comments:
1. Make sure that internal plane 1 (GP1 in your gerber set) is solid ground plane with no signal traces
2. please change "relief connect" to "direct connect" . This is very important for ground connections from components to ground pour

Regards
Brani

Hi Brani

Thank you very much for all your effort in helping.

I have made the changes on the polygon pours not to have thermal reliefs - GP1 doesn't have any track and is solid - however I have thermal relief connects on GP1 GND for soldering purposes. Shall I also have GP1 GND connections with direct contact?

Thank you in advance