• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 359 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UC3827-1: UC3827-1

Finn Hammer
Prodigy 20 points
Part Number: UC3827-1

Dear sirs.

I am working with the UC3827-1 controller, for a high voltage psu.

In the breadboard stage, I have found that the output signal of the Buck stage, pin 2, has a minimum duty cycle of around 6-7%, and a max. duty cycle of 97%.

It is the low end that puzzels me, and my question is simply: Is this normal for the chip, that it starts at 7% duty cycle, and not all the way down to 1%, or should I continue to search for a reason.

I have tried to breadboard two individuel chips, they display identical behaviour.

Supply is a well bypassed 12V

Current sense amplifier is passified by connecting pin 7 to pin 9, and pin 8 to ground.

Current error amplifier is forced low by grounding pin 13, pin 12 to Vref, and PWM reference voltage derived from Vref, ramp to pin 5 is directly from pin 18, (CT)

I have made a short video, where blue is ramp voltage into pin 5, yellow is PWN Buck output viltage @ pin 2, and cyan is the simulated voltage error signal. You can view it here:

I hope this makes sense, and am waiting your advice.

Cheers, Finn Hammer

  • 0
    TI__Mastermind 34465 points
    Hello Finn,
    I have not used this device before but hopefully I can offer you some suggestions that may help with your troubleshooting.
    The UC3827-1 buck output stage relies on a a bootstrap technique which charges a reservoir capacitor between pins V+ and SRC.
    The buck driver output BUCK charges this capacitor and you need to ensure that at minimum voltage there is sufficient stored voltage on V+ to provide gate drive to your buck switch. TI has published applications notes on how to size this bootstrap capacitor based on load and switching frequency. You can find these notses if you do a search for "high side driver bootstrap capacitor requirements"
    So my guess is that you do not have enough capacitance here.
    You can test for this easy enough enough by disconnecting the buck switch or increasing the capacitance on V+, SRC.
    The UC3827-1 is an older bipolar device and it looks like you are getting a minimum pulse width of about 1uS
    Bipolar devices are slower than the CMOS devices (UCCxxxx part numbers ) but you should still expect to see a few hundred nanosecond minimum pulse widths .

    Is the minimum duty cycle cycle causing issues with your design, for example on/off hiccuping of the supply or over voltage on the output ?

    Regards
    John
  • 0 in reply to John Griffin1
    Prodigy 20 points

    John,

    Thank you for your answer.

    I am well acquainted with the bootstrap method of supplying a gate voltage that lies above the supply rail, to the high side switch, and I am sure that the size of this capcitor is not the cause of the problem. I use a 1µF ceramic capacitor.

    Raising the supply voltage from 12V to 16V (20V is absolute max. according to specsheet) did reduce the duty cycle to 3-4%, equal to about 700nS, and I guess I can live with that (do I have a choice).

    However, I am wary of a chip that that only "kind of" performs as advertised. For example, the timing capacitor is supposed to chage/dischage between 0.5V and 3.5V. My samples only charge the timing capacitor to 2.7V before discharging to 0.5V.  Strange...

    Cheers, Finn Hammer

  • 0 in reply to Finn Hammer
    TI__Mastermind 34465 points
    Hi Finn,
    Thank you for your in depth analysis on this part and your high lighting of its performance.
    I will close this post since I believe there is no new information available.
    Please open a new post if you make any further observations.

    Thanks
    John