UCC28700-Q1: detail PWM control

Hello user4382362,

Please see the following answers to your questions.

>I tried to use auxillary winding signal as feedback, but I don't know how to control the MOS to shut down, I only know how to turn on MOS; 

Section 7.4 in the data sheet explains the opperation of the IC and where the FET will turn-on and turn-off based on the aux winding signal voltage levels required frequency and peak current to maintain duty cycle.  Please review this section and let me know if this answers your question.

>If I sample feedback signal from primary current, then where the voltage feedback connect to ?

The output voltage feedback is through the aux winding.  A voltage divider is taken of the aux winding and FED to the VS pin for this purupse.  Figure 17 will show you how to setup the voltage divider off the aux winding for sensing.  Section 8.2.2.5 will give calcualtions on how to setup the resistor dividor for VS formed by R1 and Rs2.

>the more serious question is: how I control the frequency?  (I have tested the circuit using UCC28700, finding that the frequency is variable at different load and Vin, so during simulation, i must know detail control in order for better circuit)

The UCC28700-Q1 uses frequency modulation (FM) and peak current (AMP mode modulation to control the duty cycle in a discontinuouse mode flyback.  The maximum frequency is set the primary magnatizing inductance.  Please refer to equation 25 in the data sheet for details.

The UCC28700-Q1 based on the VS at the sample point will adjust frequency and peak to control the duty cycle and output votlage.  Please refer to section 7.4.1 for descriptions of where the sample point for VS (figure 12) is and how the switching frequency and peak current (Fig. 13) will vary based on an internal voltage amplier.

Regards,

Mike

Hello user4382362,

In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer
energy to the secondary. As shown in Figure 13 it is clear there is a down slope representing a decreasing total
rectifier VF and resistance voltage drop (ISRS) as the secondary current decreases to zero. To achieve an
accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks
the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after
the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current.
The internal reference on VS is 4.05 V; the resistor divider is selected as outlined in the VS pin description.

The UCC28700 VS signal sampler includes signal discrimination methods to ensure an accurate sample of the
output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to
ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any
subsequent leakage inductance ring. Refer to Figure 14 for a detailed illustration of waveform criteria to ensure a
reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset
pedestal, TLK_RESET in Figure 14. Because this can mimic the waveform of the secondary current decay, followed
by a sharp downslope, it is important to keep the leakage reset time less than 500 ns for IPRI minimum, and less
than 1.5 μs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform following
TLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100 mVp-p at least 200 ns
before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it usually occurs
during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on VS is scaled up to the
auxiliary winding voltage by RS1 and RS2, and is equal to 100 mV x (RS1 + RS2) / RS2.

There is also an application note titled troubleshooting TI PSR controllers that you might find useful at the following link.
www.ti.com/.../getliterature.tsp

Regards,

Mike

I sample the seondary winding current, when Isec decrease to 10mA or 0, then I sample VS signal. But the present problem is when I sample VS signal, how to keep VS signal and adjust Duty when simulating? Thank you!

Hello,

The UCC28700 is not a device that you can control open loop even on the bench. So I belive this simulation is the best that you can do.

Regards,

Mike