TPS2557: Setting time for Two-Level Current-Limit Circuit

Hirokazu Takahashi

Part Number: TPS2557

Dear Team,

We are studying Two-Level Current-Limit Circuit in Figure 22.

Could you let me know the settling time for changing the current limit value at the condition neglecting the slew rate of the external FET Q1?

We want to know the worst delay time for it.

Best Regards,

Hirokazu Takahashi

over 5 years ago

0 Feifei Shen over 5 years ago

TI__Expert 3275 points

Hi Takahashi-san,

We don't have delay time spec for this usage.
The current limit is proportion to the sink current go through the limit resistor.
As long as the limit resistor network become stable, the new current limit value will apply.

Best regards,
Feifei

0 Hirokazu Takahashi over 5 years ago in reply to Feifei Shen

TI__Expert 8420 points

Hello Feifei-san

Thanks for your reply.

I can find the delay time between EN and Output in Figure 1 and 2 of Datasheet.

If we can set the external register before EN active, is it enough for the current limit setting?

If you have block diagram for current limit, please share it for us?

Best Regards,

Hirokazu Takahashi

0 Feifei Shen over 5 years ago in reply to Hirokazu Takahashi

TI__Expert 3275 points

Hi Takahashi-san,

Yes, the datasheet describe the turn on time from EN hight to output achieve 90% target voltage.

If we change the current limit, make sure it's stable before EN active, it's enough for current limit settings.

Best regards,

Feifei

0 Hirokazu Takahashi over 5 years ago in reply to Feifei Shen

TI__Expert 8420 points

Hello Feifei-san

Thanks for quick reply and support.
We want to know the setting time of current limit value at EN active condition.
Could you please simulate it?

Best Regards,
Hirokazu Takahashi

0 Feifei Shen over 5 years ago in reply to Hirokazu Takahashi

TI__Expert 3275 points

Hi Takahashi-san,
Close the thread first since already discuss in mail.

Best regards,
Feifei

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TPS2557: Setting time for Two-Level Current-Limit Circuit