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UCC27714: UCC27714 Output Latch-up in Two Transistor Forward Converter

Mark Huggins
Prodigy 20 points
Part Number: UCC27714
Other Parts Discussed in Thread: UCC28517,

I’m currently working on a battery charger implementing a two-transistor forward converter with PFC front end using TI’s UCC28517 dual controller and UCC27714 high side low side driver. I have experienced some catastrophic failures of the forward stage which on further investigation appears to be a result of latch up of the UCC27714 outputs. I have seen many instances of the UCC27714 High side driver latching in the high state with the low state driver latched in the off state, however, I have yet to capture a high and low side dual high state latch event due to the catastrophic result and difficulty of capture. On increasing the value of the gate drive resistor from 3R3 to 10R I have managed to reduce the instances of failure, which points to a dv/dt problem, but it doesn’t cure the problem and increasing the value further will push the converters efficiency out of spec. I have followed all of the UCC27714 application note guidelines (use of Schottky diode clamps, VDD filter, layout etc) but the problem remains.

The two-transistor forward converter takes the HS pin below COM ground but the datasheet claims -8V minimum compliance so this shouldn’t be a problem?

My design configuration is as follows:

Operating frequency: PWM 260kHz PFC 130kHz

Bulk Voltage: 400V ±20V (failures have occurred below 120Vdc)

HS/HB supplied from separate isolated 16V AUX supply (Bootstrap not used)

Switching FET gate pull down: 10k

Power FET gate resistor: 10R (3R3 increases failure rate)

VDD filter: 4R7 with 1uF and 100nF ceramic

PWM Output of UCC28517 driving both HI and LO inputs through separate 51R resistors and 100pF capacitors

VREF of UCC28517 driving the enable pin of UCC27714

Switching FET’s IPW60R080P7

TX clamp diodes: DESI8-060AS

TX magnetising current: 180mA

Layout points of note: UCC28517 located approx. 50mm away on daughter board, UCC27714 located across the two-switching power FET’s (as close as possible) gate source drive direct across FET pins

Are TI able to provide any further guidance on preventing the latch-up of UCC27714 outputs?

Are TI aware of the successful implementation of the UCC27714 in two transistor forward converters?

Thank you

  • 0
    TI__Mastermind 21245 points
    Hello Mark,
    The trend you see of improvement when you increase the gate resistance from 3.3 to 10 Ohms is useful information, and likely does reduce the switch node dV/dt.
    High dV/dt on the switch node can generate two concerns, one of which is the dV/dt rate on the switch node itself, the other is the current resulting from the miller charge back into the gate during switching increases with dV/dt.
    can you confirm the dV/dt you see on the switch node with the latest configuration? The driver is capable of 50V/ns which is stated in the datasheet.
    If the driver outputs have excessive overshoot or undershoot, this can result in the output in the incorrect state. I see that you mentioned that you have the schottky diodes to clamp the driver output. Confirm that the diodes are placed very close to the driver IC pins with short, low inductance trace connections.
    One other thing that can help reduce miller charge related disturbances on the gate drive, is to add additional capacitance on the MOSFET gate to source, close to the MOSFET. This additional capacitance will reduce the voltage delta on the gate to source from the drain to source charge.
    Can you confirm the VDD voltage on the driver? I see you mentioned there is 16V dedicated bias on the HB-HS. Is there a reason you are using driver bias this high? There is usually little Rdson benefit operating over 10-12V.

    Let us know if this helps, or you can post additional questions on this thread.

    Regards,
    Richard Herring
  • 0
    Prodigy 90 points
    Mark, I was having a similar problem last year due to the lack of Schottky diode clamps. You mentioned you have the clamps, hopefully in the right place . . . I needed the diodes from COM-LO and from HS-HO. The old data sheet (Aug 2015) did not show a schematic to include these clamps but instead, showed internal diodes (fig 44) which led me astray as I thought these were to be in place of external clamps. Even the text was misleading:
    Example, on pg 24 "The negative voltage of HS with respect to COM causes a logic error of HO if the driver cannot handle negative voltage of HS. However the UCC27724 offers robust operation under these conditions of negative voltage on HS."
    The new data sheet, March 2017 figure 57 now shows the clamp diodes where they are needed. Once I put these in I had no more problems with catastrophic shoot thru.
  • 0 in reply to Darrell Hambley0
    Prodigy 20 points

    Hi Darrell, I'm using the new March 2017 datasheet and have applied Schottky's on the pins you refer to and to VDD/HB. What clamp diodes did you use? I've tried BAT54 but think the forward drop may be high under my dv/dt conditions.

  • 0 in reply to Mark Huggins
    Prodigy 90 points
    I used the SD080520201R0 20V, 1A, 0805 diodes mounted very close to the pins. I first tried a smaller 500mA version but the UCC27714 still latched up. The scenario of the latch up was as follows:
    1. Bottom FET is conducting in reverse then,
    2. LO turns off, 300ns later HO turns on...
    3. Top FET supplies the reverse-recovery current for the bottom FET, Drain V starts to rise...
    4. The source inductance, Ls of the bottom FET ~5nH, is pulling 10A but this current has "nowhere to go"
    5. Ls forces part of this current thru Cgate and thru the LO pin until bottom FET turns back on with Cgate at ~4V.
    6. This current out of the LO pin causes >> 0.3V drop which somehow causes the logic of the UCC27714 to mess up and then both the top and bottom HO and LO turn on at once.
    7. Catastrophic failure.
    The top HB boost cap sometimes get's completely discharged also during this time. I've caught this on the scope a few times when I was testing at a lower voltage to avoid parts breaking....just further evidence that the internal logic gets severely messed up if HS-COM goes below 0.3V.
  • 0 in reply to Darrell Hambley0
    TI__Mastermind 21245 points

    Hello Darrell,

    Thank you for commenting on the solution you found to address the same problem that Mark Is seeing. To effectively clamp the driver outputs to the ground reference (either HS or COM) the diodes need to have a reasonably low Vf. 1A rated diodes offer lower Vf and can be found in small enough packages to allow close placement to the IC. This is what we typically use for the purpose of clamping the output driver to limit overshoot or undershoot.

    Regards,

    Richard Herring