Hi There,
In order to control the out-rush from my battery pack when connected to a capacitive load I am hoping to add an active current limiting network to the DSG FET gate to slow it's turn on. This is because currently a large capacitive load triggers the AFE SC and OC protections which renders the battery unable to power the load, the protection just cycles the output on and off for all time.
As such I am wanting to simulate the FET driving circuitry, such a simulation is very dependent on the specifics of the gas gauge's output. The data sheet for the part more or less only specifies a rise time for the output. As such my simulated driver is a very square edge with that rise time, whereas the output I see on the PCB (the simulation captures the surrounding circuitry too) has a distinctly rounded top edge. so I was wondering if you could provide me with a reference that might allow me to construct my own spice model of the output driver?
Thanks,
David
