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Question about UC1524A

Takahiro Nishizawa
Genius 5575 points
Other Parts Discussed in Thread: UC1524A

We have questions about UC1524A.

(UC1524AJ883B)

Question 1.

UC1524AJ883B belongs to UC1524A.

Is this understanding correct?

Question 2.

In datasheet p.3 "Oscillator Section",

Output pulse width is 0.5µS(typ).

If frequency is 100kHz, cycle is 10µS, High is 9.5µS and Low is 0.5µS.

Is this understanding correct?

Question 3.

Please tell us the formula about Output pulse width with frequency.

We want to know the Output pulse width for each frequency.

Best regards,

Takahiro Nishizawa

  • 0
    TI__Mastermind 24975 points

    Hey Takahiro,

    1. Correct

    2. I believe it is 0.5 us High and 9.5 us low, however note that the output is a ramp and not a square wave.

    3. There is no equations for Output pulse width vs. frequency

    Thanks,

    Daniel

  • 0 in reply to Daniel Hartung
    Genius 5575 points
    Thank you for your answer!
    We have new questions about UC1524A.
    (UC1524AJ883B)

    Question 1.
    In datasheet p.1 block diagram,
    Please tell us the output of E/A when input voltage of pin 1 is 4.9V and input voltage of pin 2 is 5.0V.

    Question 2.
    In datasheet p.1 block diagram,
    the voltage of C/L is 0.5V when 4 pin is GND and 5pin is GND input.
    Because maximum value of output swing(current limit amplifer) is 0.5V.
    Is this understanding correct?

    Question 3.
    In datasheet p.1 block diagram,
    Please tell us the function of COMP.

    Question 4.
    In datasheet p.1 block diagram,
    How does PWM LATCH work.
    Please tell us the relationship between COMP and PWM LATCH.

    Question 5.
    In datasheet p.1 block diagram,
    Please tell us the operation of FLIP FLOP.
    This IC divide at the time of startup.
    So output frequency of FLIP FLOP is half.
    Is this understanding correct?
    Output of FLIP FLOP is two.
    Is upper side of FLIP FLOP High?
    Is lower side of FLIP FLOP Low?

    Best regards,
    Takahiro Nishizawa
  • 0 in reply to Takahiro Nishizawa
    TI__Mastermind 24975 points

    Hey Takahiro,

    1. This is a value that I would have to measure, and I am unable to.

    2. This is a value that I would have to measure, and I am unable to.

    3. COMP is the error amplifier/ C/L output which will provide a voltage level that will change the duty cycle of the device.

    4. The PWM Latch compares the voltage level at COMP to an oscillator ramp which the latch changes into a square wave.

    5. Generally when I have seen flip flops used for this type of device, the flip flop is used to offset the outputs of the controller. Its likely the two outputs are inverted.

    Thanks,

    Daniel