UC1825A-SP: UC1825A-SP

Hey Jason,

Clamping the E/A OUT is clamping the maximum duty cycle.

The device will use the first limit it hits. Either the duty cycle limit will terminate the pulse or the current limit will terminate the pulse.

Thanks,

Daniel

Thanks Daniel

Jason

Daniel,

Is there an internal delay on the Current Limit circuit that could cause the PWM Comparator control the duty cycle limit first ?

Thanks

Jason

Hey Jason,

Theoretically if both tripped at the same time where will be some variation.

The datasheet specifies that the Ilim has and input to output delay of 50 ns typical and 80 ns maximum.

The datasheet also specifies that the COMP to output delay is 50 ns typical and 120 ns maximum.

This means if both tripped at the same time, depending on variation there could be one tripping slightly before the other.

Thanks,

Daniel