LM5109B: How much maximum gate charge can be apply on output of IC?

Hello Abhi,

Thank you for the interest in the LM5109B. I am an AE with the High Power Drivers group and will address your questions.

The main consideration for the gate charge that the driver can support is the power dissipation from the gate drive and resulting temperature rise from this power dissipation. Refer to the LM5109 datasheet, http://www.ti.com/lit/ds/symlink/lm5109b.pdf, section 8.2.2 Detailed Design Procedure.

The ability to drive a given gate charge, from a thermal standpoint will depend on the package used, as the SOIC package junction to ambient thermal resistance is 117.6 ^oC/W where the WSON package is 42.3 ^oC/W, this will determine how much power can be dissipated for a given temperature rise over the maximum ambient temperature of the board. Also the switching frequency, VDD voltage, and gate resistance are the parameters that determine the gate drive power dissipation. For the power dissipation refer to equations 12 thru 14 in the datasheet.

I will make some assumptions to show some examples below to show maximum switching frequency for a given gate charge. I will concentrate on losses from driving the MOSFET Qg since this will dominate the power loss. The datasheet equations show additional losses from quiescent current and level shifter. VDD=12V, gate resistance is 0 which means all gate drive power is dissipated in the gate driver IC, SOIC package, board ambient temperature is 70 ^oC.

Maximum temperature rise is 125^oC-70^oC=55^oC. Maximum power dissipation is 55^oC/(117.6^oC/W)=467mW.

Gate drive power for both LO and HO (with no gate resistance) is: Pgd=2 xVDD x Qg x Fsw, rearrange for Fsw. Fsw=Pgd/(2 xQg x VDD). For 400nC Fsw= 48.6kHz, for 700nC Fsw=27.7kHz, for 900nC Fsw=21.6kHz.

Gate drive rise and fall time is also a consideration. Determine if the gate drive strength of 1A will provide the Vgs rise and fall time desired. A simple estimation is to determine equivalent capacitance based on Qg. For 200nC usually specified at 10V the equivalent capacitance will be 20nF. Using dt=CdV/I, dt will be 240ns with a 200nC gate charge. If you are operating at high frequencies or with the larger gate charge FETs of 700nC to 900nC you should consider a driver with higher gate drive strength to reduce the switching times.

Please confirm if this addresses your questions, or you can post additional questions on this thread.

Regards,

Richard Herring