TINA/Spice/LP2951-N: Output Discharge on shutdown

Further investigation shows that the input voltage rises as the output voltage falls, in fact pushing it up above the supply voltage. 

Hi Aidan,

Can you send me your simulation file? I put together a quick sim and and not seeing the behavior you describe.

That being said, the LP2951 does not have an active pull-down circuit. Any discharge path when disabled would be a function of leakage paths or an external divider if used.

Hi John,

Please excuse the fact that I have changed the regulator that I am simulating with. I needed lower noise figures. However the same strange behaviour is still evident. I am at a loss to understand what is happening, both the LP2951 and the LP38798 TINA models seem to show the same behaviour.

I placed a diode on the VIN pin thinking this would prevent any reverse current. This is not what I want finally but I am trying to understand what is going on with the simulator. 

As you will see from the attached TINA file. Even if I hold the input voltage steady, as soon as the enable input falls below threshold there is a rapid rise in the voltage seen on the input to the regulator. The output cap is discharged into the input cap. If the size of the output cap is increased the reverse current increases.

If the input cap is disconnected the voltage on Vin Pin shoots up to over 100V, still discharging the output cap into the diodes capacitance ( I assume).

I have included the same simulation using the LP2951 also.

Is there something obvious I am missing here? Am I doing something dumb. This is surely not the behaviour I expect.

Any comments?

Aidan

LP2951_strange.tsc

LP38798_strange.tsc

HI Aidan,

I confirmed the behavior with the models you have. However, I do not see this issue downloading the current model with the LP2951 on TI.com.  The LP38798 model I downloaded has the same result you observed.

I recommend trying an EVM as I think you will see the behavior you are expecting.

I hope this helps.

Regards,

LP2951 Test.TSC

Putting a diode in series with VIN is a common way to prevent reverse current.

Hi John,

I appreciate that you have  taken a look, however both the models I have been using are both recently downloaded from your website, they are the latest. 

I understand that EVM will finally be needed, but the problem is that the simulations I am working on are dependent. When one competent has a significant deviation from reality this makes it difficult to fully simulate as an integrated whole. By simulating just parts of a circuit, it is all too easy to overlook the interactions between cascaded elements.

Therefore as much as I would like to agree with you I would still suggest that unless you can identify something fundamentally wrong with my circuit layout, then it seems to me that the model is simply incorrect (however past experience with TINA models is a mix of both, most often it is my mistake, but not always). In this case it is not a matter of precision, but rather a behavioural issue. I have never seen a voltage regulator that dumps its output charge into the input circuit when the input voltage exceeds the output voltage, but that is what seems to be happening.

Perhaps you could take a little more time to investigate further. I would be more than happy to have my error identified. It is more than possible that I have overlooked something. I would much sooner look stupid than discard the IC because I can't get the simulation to play ball. Please help.

Many thanks

Aidan

HI Aidan,

I have already put in the request to get behind what is going on with these models. They clearly have an issue. I do not believe your circuit is the issue.

This may take a few business days to resolve.

Thank you for your patience.

Hi Aidan, 

This is just to let you know we are still waiting for a response from the modeling team. Our next update will be on 7/29/2019. 

Regards, 
Jason Song

Hi Jason,

Sorry to be inpatient, however this issue has been causing me difficulty to complete my simulations. therefore I did some further investigations myself. I thought I would share my findings. 

I used the LP38798 TINA model as this is unencrypted and I was able therefore to take a look at the SPICE behind things. (OPENSOURCE GOOD!!!!).

What I discovered is that within this macro there seems to be a generic subckt called LDO_BASIC. I assume therefore several of your models including the encrypted ones use the same.  (CLOSEDSOURCE BAD!!!!).

:)

This subckt uses a current controlled current source to model the output current to the input current. Reflecting the output current onto the input side of the regulator. This is driven by a current seen at a node downstream of the output voltage source after it has been forced through a resistance 'rout' ~ 10m Ohm. I assume this is modelling the output resistance of the pass element. All is well until either EN falls below threshold or UVLO falls below threshold. When this happens the output voltage source is switched off and drops to zero volts. However the output voltage as seen on any external output capacitor is now placed across the same 'rout' and current flows through 'rout' to a 0V point (i.e. opposite direction to when the output cap is charged). This current is reflected onto the input, which, if blocked by a series diode on the VIN pin, forces the voltage at the VIN pin to rise rapidly to a silly impossible value. Even without the series blocking diode on the input this current still must be sinked by any input circuit. This same 'rout' therefore also rapidly discharges the output capacitor regardless of the voltage seen on VIN because the current source is not taking any account of the voltage at VIN. This is clearly not realistic.

Anyway, to overcome the issue, I reworked the LDO_BASIC subckt and replaced the simple 'rout' resistor with a voltage controlled resistor. With this modification whenever the LDO is active (VIN>UVLO) and enabled (EN > EN_thre) the voltage controlled resistor acts just the same as 'rout'. However if either of these conditions is not satisfied, the VCR is made very high 100MEG. This prevents any significant current from flowing from the output cap through this resistor to the 0V point and subsequently the reflected input current is negligible. In reality it should be zero and this could be made so, by simply preventing the current source from reflecting reverse currents, but that's another step.

Also this does not model what the internal regulator circuit does with Vout higher than Vin, or for that matter if Vout is forced higher than the voltage source in the regulator by for example an external voltage source applied to Vout. However from what I can tell the LDO_BASIC subckt does not do this anyway. So to expedite my simulations I have simply placed a Schottky diode between output and input, in the classic configuration.

I have shared the modified macro, which for me has at this stage resolved my simulation issues. Which BTW was related to how long I get between signalling a PSU fail state (disabling the LDO) and the 3V3 volt dropping below minimum voltage on an MCU. i.e do I have enough time to gracefully shut down the MCU before the 3V3 line collapses. With the LDO sucking all the energy out of the output caps this was clearly not helping.

All the best

Aidan

LP38798-ADJ_modified.TSM

Hi Aidan,

Great work, it's pretty amazing that you fixed the LP38798 model on your own. I really appreciate your great insights on the problems with the current model. I am sure we could apply the same technique on the other models that have similar problems including the one for LP2951-N. 

I have bookmarked your post and saved your modified model for LP38798. We will review the changes you made, and share your work with other people who encounter similar issues. Again thanks a lot for your work. 

For your new questions below, please see my comments: 

Which BTW was related to how long I get between signaling a PSU fail state (disabling the LDO) and the 3V3 volt dropping below minimum voltage on an MCU. i.e do I have enough time to gracefully shut down the MCU before the 3V3 line collapses. With the LDO sucking all the energy out of the output caps this was clearly not helping.

--I assume you are talking about the application with LP38798. If an LDO does have a power good pin to monitor its own output rail, it would be easy to figure out the timing since PG timing is normally defined in a datasheet. For this device, there is no power good pin. I think you were asking how much time you have to turn off the MCU from the time the LDO sensing the disabling signals, correct? I don't see there is an active discharging circuit in this device, and this means when the device is being disabled, the voltage on the output pin is discharging by the leakage or the load on the output. A bigger output cap should allow a longer discharging time. You could also use the size of the cap and the load current to estimate the discharging time. Does this make sense? 

Regards, 
Jason Song