C6 - 1uF
R7 - 536Ohm
R8 - 2.2kOhm
R9 - 5.6kOhm
R10 - 2.7kOhm
CHARGE_EN - 1.892v-1.352v or GND controlled by OR Gate (SN74AUP1G32DCKR)
I just wanted to check my schematic because the datasheet regarding the TS pin could be more clear. Using R9 and R10 as a voltage divider when the OR Gate is high should provide the TS pin with .62V-.44V which should be within range of normal operation, and when low provide 1.82kOhm (5.6kOhm and 2.7kOhm in parallel) of resistance to GND which would disable the chip based (equivalent to 75-80 degrees C) on the 10k NTC thermistor as mentioned in the datasheet. Am I missing something or is this correct operation. Thanks in advance!