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LP87702-Q1: LP87702-Q1 WD/Driver related questions

Part Number: LP87702-Q1
Other Parts Discussed in Thread: LP8770Q1EVM, LP87702, AWR1642

Hi TI professors, here are some questions about LP87702-Q1, need your help on these

1.Does TI have a packaged Driver officially for reference, instead of using IIC manual control registers?

2. If WD_LOCK is factory default OTP status? and will be automatically set to 0 when each restart.

3. There are two ways to disable WD according to the datasheet:

    a) set WD_DIS_CTRL to 1, and WD_DIS pin to high level (Due to customer circuit setting, WD_DIS floating, this way not applicable)
    b) set WD_RESET_CNTR_SEL to 0x00, at which point the system restart is disabled (IF it is because of this, so that the WD does not take effect when factory delivery?)

4. How to understand and handle WD_LONG_OPEN_TIME?


  • Hi Kun Yuan,

    1) No we don't have any drivers for LP87702-Q1 device. If you use LP8770Q1EVM, you could use EVM GUI to control device, but otherwise it is thru I2C writing.

    2) WD_LOCK is lock bit for watchdog controls. It locks all controls to watchdog in registers WD_CTRL_1, WD_CTRL_2. Lock bit also locks itself. Once lock bit is written 1 it cannot be written 0. Only reset can clear it. 0 - Not locked 1 - Locked WD_STATUS register is not affected by WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK=1. Default 0x0

    3) a) correct. If WD_DIS_CTRL = 1 WD_DIS_PIN (multiplexed with CLKIN pin (22)) can be controlled WD disable/enable. If WD_DIS_PIN high, disabled. If low, enabled.

    b) WD_RESET_CNTR_SEL setting will not disable WD. If setting is 0x00 and when WD expired (no WDI pulse) it will give pulse to WDRESET pin and start to new long open time (typically 5s). If WDI still not available and WD expired again, WDRESET pulse provided. This loop continued until WDI provided. 

    4) WD_LONG_OPEN_TIME is the time, how long WD wait WDI signal during startup. Long open, close and open window periods are independently programmable as shown in datasheet table 4. When long open or open window expires before WDI input is received, watchdog enters WD Reset state. Also when WDI is received during close window, watchdog enters WD Reset. Long open period can be extended by a I2C write to WD_CTRL_1 or WD_CTRL_2 register.

    Example. WD_LONG_OPEN_TIME = 5s, WD_CLOSE_TIME = 100ms, WD_OPEN_TIME = 100ms. In startup long open time start. If for example after 2s WDI pulse given, WD moves immediately to close time(100ms). After close time, open time starts (100ms) and that time WDI pulse need provide again. So in other words close and open time define WDI pulse frequency.

    Hope this help to understand more WD behavior in LP87702 device, thanks


  • Thanks Tuomo for your answering. Still have some question here:

    The question is based on these word condition:

    1.LP87702 is set to OTP by default;

    2.WDI_IN(PIN7) connect to AWR1642 MCU IO, no feed dog operation

    3.WD_DIS(PIN22)floating,(tested as LOW actually)

    According to datasheet, WD should be "Open" status, WD_RESET(PIN6) should have WD Pulse signal output;

    but now we only can detect LOW when Powered on, and then is continuous HIGH. See below picture:



     So, the questions are:

    1. Is WD function turned on in this state? If not, how to configure a register to open?
    2. How to configure CLKIN/GPO2/ WD_DIS as WD_DIS?
    3. LP87702 feeding method? Feed dog via WDI pin or IIC interface?


  • Hi,

    Sorry for late reply, I was on vacation last week.

    WD polarity can be programmed and if device you are using is LP87702D-Q1, WD_RESET has been set Open Drain output and Active LOW. That means, when reset is active, signal is LOW as you see. 

    With the above device, WD should be configured already to WD disable with CLKIN pin. CLKIN pin LOW enabled, pin HIGH disabled.

    WD feed need to be provided to WDI pin.