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LMZ14203H: Need worst case Gain/Phase margin analysis including temperature range and EOL aging

Jim Brinkhurst1
Mastermind 44220 points
Part Number: LMZ14203H

Hi Power Team!

My customer has an LMZ14203H circuit and needs to know the worst case stability over the following conditions:

1. Vout : 12V
2. Load: Nominal 0.2A, Max: 0.75A (if going in pulse skipping, what freq and ripple voltage)
3. Vin: 24V
4. Worst case phase margin (temp (-40deg to 85 deg, aging – BOL, EOL)
5. Worst case Gain margin (temp (-40deg to 85 deg, aging – BOL, EOL)
6. Input filter: Pi filter : 22uF – 10uH -22 uF (X7R caps)
7. Output filter: 3*10uF IIel 22uF (All ceramics) 

Can you help with this analysis? I don't know how to configure the WEBENCH Power Designer Tools to provide the needed stability analysis with these components.

Best regards,

Jim B

  • 0
    TI__Guru 50120 points

    Hi Jim,

    This request sounds like quite a bit of bench test including thermal stream control. I don't think there is a way to simulate this. Webench does not account for thermal shifts. As note that the TI Santa Clara site is still close for the upcoming pandemic future. Because of this, I have limited to almost no access to the lab. 

    I would suggest providing the customer with an evaluation board to test their specific condition. I would also like to mention that the part is expected to be stable as long as the output capacitance and ESR range are met over temperature. The table in Figure 43 provides the typical recommended component selection, capacitor ESR, and input/output range for a stable operation.

    Regard,

    Jimmy 

  • 0 in reply to Jimmy Hua
    TI__Mastermind 44220 points

    Hi Jimmy

    The customer's current design parameters are below. It looks like their output capacitance isn't quite large enough, and has an ESR lower than optimal for stability.

    I believe if they increase Cout: Min to 47 uF and ESR: Min to 1 mOhm their system should be stable over product lifetime. Can you confirm?

    1. Cout: Min : 30uF , Max : 50 uF
    2. ESR: Min: 0.3 omhm, Max: 4 mohm
    3. CFF: 10 KPF +/ 20%
    4. Vin: 18V-36V
    5. Vout: 12V
    6. Load: 50mA to 750mA

    All other parameter is same as shown in datasheet Figure 46.

    If possible, please let us know worst condition phase and gain margin with current and updated Cout parameters.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Guru 50120 points

    Hi Jim,

    The worse case condition will be at 750mA load condition. As for the output capacitance I don't think 30uF would be an issue because of the low load current. The 47uF is used on the LMZ14203HEVM for a similar voltage condition but for a much higher load current up to 3A. However to stay consistent with the datasheet, you can recommend 47uF. 

    As for the phase and gain margin, this is a COT device that doesn't have an AC model. Because of this I would recommend providing the customer with an EVM for them to test stability on their end as mentioned above. 

    Regards,

    Jimmy