Other Parts Discussed in Thread: TPS43331-Q1,
I'm designing the power supply of a Jacinto6-based board and I'm using the TPS43331-Q1 as a first-stage regulator to provide 3V3 and 5V0 to my circuit. Unfortunately, after reviewing the datasheet I still have some doubts I hope you can help me with:
Regarding its VIH(th )and VIL(th).... which one of the following assumptions are correct?
- Being ENA/ENB HIGH, It will remains HIGH until the voltage decreases to VIL,th = 0.7V
- Being ENA/ENB LOW, It will remains LOW until the voltage increases to VIH,th = 1.7V
- Being ENA/ENB HIGH, It will remains HIGH until the voltage decreases to VIH,th = 1.7V
- Being ENA/ENB LOW, It will remains LOW until the voltage increases to VIL,th = 0.7V
If neither of the above assumptions are correct, then How is the exact behaviour of these thresholds?
Regarding its relation with PGA/PGB...
What happens when a ENABLE pin is asserted LOW?
- Is the regulated output immediately turned OFF or is there any delay present?
- Is the Power Good output immediately turned OFF or is it affected by the tdelay delay?
VIN(Min) and VIN(Threshold)
According to the datasheet, the OPERATING voltage range (after initial start-up) is 4V - 40V and the UNDERVOLTAGE limit is 3.6V. With this information what I understand is:
- The buck regulators will work in the range 4V - 40V. Below 4V it will stop regulating (bucks will shutdown -> PGA/B asserted low INMEDIATELY, no voltage in the regulated outputs)
- The rest of the internal functions of the chip will work up to 3.6V
However, In the "7.3.5 UVLO and Overvoltage protection" section it specifies the following: "Once it has started up, the device OPERATES down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout disables the device." With this explanation what I understand is:
- The buck regulators will work in the range 3.6V - 40V instead of the defined 4V - 40V because it says the device will OPERATE down to 3.6V
And in the "5 Pin Configuration and Functions" section it specifies the following related with PGA/PGB: "An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value or if either VIN or VBAT drops below its respective undervoltage threshold" With this explanation what I understand is
- The buck regulators will work in the range 3.6V - 40V instead of the defined 4V - 40V because it says its PG outputs will be asserted low when the UVLO is reached instead of VIN,min.
So in the end, Which voltage range is the real one? And if neither of my assumptions are correct, then Which ones are the exact differences between VIN,min and VIN,th regarding the behavior of the device?
Regarding its tdelay...
- Does this delay only affect the PGA/PGB outputs?
- What is the meaning of the following explanation given in the "18.104.22.168 Power-Good Outputs and Filter Delays" section? "Use of this delay can pauses the delay of the reset"
- Which delay is that "delay of the reset"? Which functions are affected by this delay?
Operating point doubts
Finally, In order to fully understand the behaviour of the device in my design, I have some doubts related with some specific operating points.Let's assume the device is working under an initial VIN = 24V and then the power supply is abruptly removed from the circuit so the VIN voltage starts decreasing quickly. What would happen with...
- 3V3 buck regulated output
- 3V3 buck PG
- 5V buck regulated output
- 5V buck PG
... in the following situations?
- VIN = 5.5V
- VIN = 5V
- VIN = 4.6V
- VIN = 4V
- VIN = 3.8V
- VIN = 3.6V
- VIN = 3.3V
- VIN = 2V
NOTE: The TPS43351-Q1 schema used is the same that is present in J6-plus EVM
Thank you very much in advance for your valuable help!