This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS62262: How much undershoot voltage is allowed at SW terminal?

Part Number: TPS62262

 Hello guys,

 One of my customers is evaluating TPS62262 on their own board for their new products.

 In their evaluation, they found SW terminal went down to about -1.2V during less than 50ns.

 They know the cause is inductor current flow into the parasitic diode of low side internal FET when both FETs of high and low side are turned off.

 But they want to know how much undershoot voltage and duration are allowed.

 Could you please give me the voltage and duration?

 Your reply would be much appreciated.

 Best regards,

 Kazuya.