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UCC21520-Q1: UCC21520-Q1 min. dead time

Vladan Lazarevic
Prodigy 30 points
Part Number: UCC21520-Q1

We are considering your UCC21520-Q1 drivers for our future designs and I have a question about the minimum dead-time that can be reproduced correctly by the driver. What is the minimum dead time that could be used, but still to avoid overlapping between the signals at the driver's output (due to some mismatch of the propagation delay times)? We do not use Rdt to set the dead time, it is done by the control unit externally (for both INA, INB).

Thank you very much in advance!

  • 0
    TI__Guru**** 189399 points

    Hi, Vladan,

    Welcome to e2e, and thanks for your interest in our devices.

    If you tie DT to VCCI, then the deadtime will be set by your controller. There is no minimum dead time in this case, as you mentioned, it is possible for outputs to overlap for system architectures that require that to happen.

    Let us know if you have further clarification. Otherwise, please press the Green button to let us know this question is resolved.

  • 0 in reply to Don Dapkus
    Prodigy 30 points

    Hi Don,

    The overlap in this case must be prevented in order to avoid shoot-through of the power transistors (voltage-source converter). I'm particularly interested in a dead time of 50 ns (at fs = 150 kHz), so it would be nice to know if the driver can operate for this value of dead-time without overlapping the outputs.

    Thanks in advance!

  • 0 in reply to Vladan Lazarevic
    TI__Guru**** 189399 points

    Hi, Vladan,

    Your controller is generating the deadtime, right? If so, there is no limitation on our side.

  • 0 in reply to Don Dapkus
    Prodigy 30 points

    Right, but due to mismatch in the propagation delay times, the output signals may overlap, which is dangerous for the power stage. There is a minimum dead-time (dt_min) that can be reproduced correctly, otherwise the output signals will overlap due to the propagation delay time uncertainty.  It is not clear from the Datasheet what is the value of dt_min and I'm still waiting to receive the answer about that value.

    Thanks in advance!

    Best regards,

    Vladan

  • 0 in reply to Vladan Lazarevic
    TI__Prodigy 460 points

    Hi Vladan,

    Thank you for following up. I work as an Applications Engineer on the High Power Drivers group and can help answer your question.

    For a minimum dead time, you would need to consider the sum of your pulse width distortion and channel-to-channel delay matching, each with maximum values of 5ns as specified in Section 6.10 in the datasheet:

    You would also need to consider the differences of rise and fall time for a channel, and this depends on the load being driven. Once you have those values, you would add these to the 50ns to provide the necessary margin (assuming worst case) for avoiding shoot through.

    If this answered your question, could you please press the green button? If not, feel free to follow up with more questions.

    Best regards,

    Liban Hussein

     

    Check out our training series on high power drivers here! These videos are great for anyone and cover everything from the basics up to design considerations for various power systems.

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