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TPS54824EVM-779: Application problem

Yadong Duan
Intellectual 970 points
Part Number: TPS54824EVM-779
Other Parts Discussed in Thread: TPS54824, TPS54A24

During the EVM test, it was found that when PGOOD outputs no load during the power-down process, a voltage of 1v will be generated after 1 second. The output voltage is very low when the output is loaded. Where does this voltage come from?

The blue one is PGOOD. Pink is PGOOD PULL UP

  • 0
    TI__Mastermind 35115 points

    Hi Yadong,

    I suspect what is happening is the input voltage is dropping low enough for the TPS54824 to not have sufficient voltage to keep the internal PGOOD FET turned on. This limit is given by the Minimum VIN for valid output spec on page 6. If Vin drops below 0.7V typical the PGOOD FET is no longer able to the pin below 0.5V when sinking 4mA.

    I will guess channel 1 is the input voltage? It does look to be <1V when the PGOOD voltage starts to float up.

    Anthony

  • 0 in reply to Anthony F
    TI__Intellectual 970 points

    But shouldn't PGOOD be less than 0.5 in this case? I think the test feels like charging and discharging a capacitor. The balance process between parasitic capacitance and output capacitance.

  • 0 in reply to Yadong Duan
    TI__Mastermind 35115 points

    Hi Yadong,

    The spec in the datasheet is just one point on an voltage vs current curve for the power good pull-down FET. Luckily we have Vin vs Ipgood curve for this FET in the TPS54A24 datasheet. The power good pin design is identical in the TPS54824 and TPS54A24 devices.

    Edit: I noticed the spec is a little different between these two devices. Even though the numbers aren't identical, the shape of this curve will be the same.