TPS3851: TPS3851 : Questions about /WDO assertion

Hi Si Yoon,

Apparently, the attached pictures did not come through.  Can you try to resend them again?

Thanks,

Ben

Dear Ben Chan
Thank you very much for your response.
It seems that the picture was not delivered due to an error.
I will attach a picture of the above question and ask again.
Thank you.

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Dear TI Team,

I have some questions about the WATCHDOG TIMER IC.

The WATCHDOG circuit is composed as follows.

The experimental results are as follows.

(b) It is a situation where the Watchdog timeout occurs after nRST=about 70s has passed before the section.

It is connected with'SYS_RST = /RESET pin, SET1 = SET1 pin, MR = /MR pin, WDO = /WDO'.

Question 1. SYS_RST(/RESET) slightly falls as much as the section where MR LOW becomes, then fixed tRST=200ms low and then turned high again.

                   What is the voltage drop in section (b-a)? Is it right waveform?

Question 2. The section where /MR changes from Low to High is known after the /RESET signal passes tRST. Is it correct? In this image, it seems that the tRST and /MR High progress intervals are similar.

Question 3. Asks whether the timing of /WDO operation is also normal.

Thank you very much.

Hi Si Yoon,

Can you tell me why both /RESET and /MR have a RC time constant type waveform?  Is power rail being shut off as well?  Looking at SET1 signal, I am guessing that the power rail looks to be off.  Can you provide a scope shot of the power rail?  Is the MR pin floating?  

For question 1, the voltage drops depends on how much capacitance you have on the VDD rail and the pull-up resistor you are using in the application.  Both waveforms appear to look correct.

For question 2, I don't think that is tRST.  /RESET went low because the power rail must have gone below VIT-.  The time when /RESET is low is tRST.  See picture below:

For question 3, the /WDO looks correct.  The picture below shows what you have once the power rail is restored.

Ben

Hi Si Yoon,

Here is the second picture.  It looks like it didn't make it in the previous post.

Thank you very much for your answer.
First of all, /RESET is only 10K pull-up as in the attached circuit, and /MR is 1uF Cap is connected Line-to-GND.
Also, when WatchDog timeout occur, all power rails go down.
The power rail is designed to go down by design, and unfortunately, we cannot provide a scope shot of the power rail.
I'm very sorry.

May I ask additional questions?

Q1. If, /MR is low, /RESET makes the condition to assert low, and if VDD goes below VITN, it becomes Low after tRST-DEL,
and If, /MR is High and VDD is higher than VITN+VHYST, /RESET changes to High after tRST.

Is the flow of motion I understood correct?

Q2. Then, if VDD is 3V3, is there a way to calculate the typ values ​​of VITN and VHYST? I looked at the datasheet and couldn't find it well.

Q3. VITN is a negative threshold voltage, known as a voltage criterion that distinguishes whether it is Voltage high or low, or a value that cannot be guaranteed. But, Hysteresis voltage (VHYST) I don't understand well. Can I ask you to explain this?

Q4. Finally, as seen from the following phrase, when a watchdog timeout occurs, WDO becomes low (assert) during the set tRST.

It doesn't make sense to look at the scope shot I took.
Is it asserted low until tRST starts, and then, when /RESET is low for nRST, WDO is in High Impedence state?
Can you explain?

Thanks for your kind response.

Hi Si Yoon,

Please see my answers in green:

Q1. If, /MR is low, /RESET makes the condition to assert low, and if VDD goes below VITN, it becomes Low after tRST-DEL,

and If, /MR is High and VDD is higher than VITN+VHYST, /RESET changes to High after tRST.

Is the flow of motion I understood correct?

Yes, your understanding is correct.

Q2. Then, if VDD is 3V3, is there a way to calculate the typ values ​​of VITN and VHYST? I looked at the datasheet and couldn't find it well.

Please refer to pg. 22 section 11.1.1 Device Nomenclature.   The values of VITN depends on which TPS3851 you are using.  For example, if you are using TPS3851G30EDRBR, the VITN threshold is 3.0V with an accuracy of +/- 0.8% and hysteresis voltage of 0.5% of VITN.  See picture below:

Q3. VITN is a negative threshold voltage, known as a voltage criterion that distinguishes whether it is Voltage high or low, or a value that cannot be guaranteed. But, Hysteresis voltage (VHYST) I don't understand well. Can I ask you to explain this?

VITN is a negative threshold voltage that describes when VDD has fallen past the VITN threshold and initiates an assert signal on /RESET.  VITN is a spec that has limits describe on pg. 5.  To understand VITN, please see below:

Q4. Finally, as seen from the following phrase, when a watchdog timeout occurs, WDO becomes low (assert) during the set tRST.

It doesn't make sense to look at the scope shot I took.
Is it asserted low until tRST starts, and then, when /RESET is low for nRST, WDO is in High Impedence state?
Can you explain?

Yes, /WDO is in a high impedance state because according to the timing diagram below, When /RESET signal is asserted low, the /WDO pin goes to a high-impedance state.  Your scope photo shows /WDO going when /RESET is asserted low.  Because the application allows the power rail to power down, TPS3851 will turn off causing the watchdog timer to be non-functional (no VDD). The timing diagram below shows it clearly.

Please let me know if you have need more clarification.  Thanks!

Ben

Thank you very much for your answer.
The power of VDD is provided individually,
In the current circuit, /WDO is in a state of 10k pull-up, and it is additionally connected to EN at the main power rail. When /WDO goes low, all power except VDD of WatchDog IC is turned off.

Q4. I would like to inquire in more detail about this.

Q4-1. When VDD keeps turning on, can I inquire about the /WDO operation flow in more detail?

Q4-2. In the timing diagram, /WDO is VDD, /RESET High, WD is low while t=tWD, /WDO seems to remain low for tRST. Is the operation flow correct?
Looking at the current scope shot, /MR changes to Low, and after that, /WDO remains low (81ms=not nRST) and then changes to High.
It is difficult to understand when compared to the datasheet timing diagram in the current situation.
Can you explain?

Q4-3. /WDO is specified in the datasheet as being asserted low during tRST, but if the WatchDog IC is turned off, or if the power rail is turned off in an application or circuit, as in the attached scope shot, it will be low in a shorter time than the tRST in the datasheet. Can it be?

Q4-4. When the Cap was connected to /MR by Line-to-GND and the capacity value was changed, the time to keep /WDO low changed. Can I ask why?

Thank you all the time for your responses.

Hi Si Yoon,

I am quite confused with the statement:

"In the current circuit, /WDO is in a state of 10k pull-up, and it is additionally connected to EN at the main power rail. When /WDO goes low, all power except VDD of WatchDog IC is turned off."

In the attached scope photo it shows that the power of VDD to the TPS3851 is being turned off. 

Please see my answers (green) to your questions below:

Q4. I would like to inquire in more detail about this.

Q4-1. When VDD keeps turning on, can I inquire about the /WDO operation flow in more detail?

During startup, the /RESET signal is asserted and the WDI input signal is ignored.  Therefore, /WDO is in a high impedance state and will be pulled up by the pull-up resistor to VDD. 

Q4-2. In the timing diagram, /WDO is VDD, /RESET High, WD is low while t=tWD, /WDO seems to remain low for tRST. Is the operation flow correct?
Looking at the current scope shot, /MR changes to Low, and after that, /WDO remains low (81ms=not nRST) and then changes to High.
It is difficult to understand when compared to the datasheet timing diagram in the current situation.
Can you explain?

Are you referring to this portion of the timing diagram?

Yes, the operation flow that you have described above sounds correct. 

Looking at the scope photo, both VDD and WDI waveforms are missing so it is difficult to comment on what is happening with the watchdog.  Base on the scope photo, my guess is: 

VDD went below VITN.  See picture above.  Once VDD goes below the VITN threshold, /RESET goes low for tRST, which is seen in the scope photo.  Also, is it safe to say that the 81ms measured in the scope photo the time when VDD rail is turned off?  Is WDI pin low/high/high impedance when /WDO goes low?  Is it possible you can share the schematic with me?  

Q4-3. /WDO is specified in the datasheet as being asserted low during tRST, but if the WatchDog IC is turned off, or if the power rail is turned off in an application or circuit, as in the attached scope shot, it will be low in a shorter time than the tRST in the datasheet. Can it be?

Yes, /WDO can be shorter than tRST if a power cycle is to occur on the watchdog IC.

Q4-4. When the Cap was connected to /MR by Line-to-GND and the capacity value was changed, the time to keep /WDO low changed. Can I ask why?

The bigger the capacitor, the longer /MR stays above VIL.  The spec for VIL is listed in the datasheet as 0.25V max which means in order for /MR to be asserted high, the /MR pin must go below 0.25V.

Ben 

Thanks for your reply.
It really helps a lot.

Would it be okay to ask more questions

I cannot share a detailed circuit, but to put it briefly, /WDO and EN of the 3.3V power line are connected, and the power rail that can be controlled by /WDO is all the 3.3V connected to /MR.
3.3V_2 is an independent power supply, and this power supply is connected to /WDO, /RESET, and VDD respectively. SET1 and WDI operation is the same as datasheet.

In this circuit, I think the /WDO operation flow seems to depend on the state of /MR.

1. It seems that /WDO is controlled by /MR, but the low assert of /WDO does not last for nRST. For this reason, it is said that this may occur when the VDD Power Rail is turned off, but there are only two pins where the Power Rail is turned off, /WDO and /MR, which are affected by 3.3V_EN. Can you see why /WDO doesn't hold for nRST in this situation now with Power rail turn off?

2. 2.2uF Cap is connected to /MR by Line-to-GND.
If this value is reduced to 1uF, the /WDO Low assert time decreases, but if this value is increased to 4.7uF or more, the following abnormal behavior occurs. There seems to be a problem with timing, In conclusion, the system does not reboot even after a time out occur. Timing seems to have a problem, can you check it once?

Thank you so much for your answer.

Hi Si Yoon,

Please see my response in green.

In this circuit, I think the /WDO operation flow seems to depend on the state of /MR.

1. It seems that /WDO is controlled by /MR, but the low assert of /WDO does not last for nRST. For this reason, it is said that this may occur when the VDD Power Rail is turned off, but there are only two pins where the Power Rail is turned off, /WDO and /MR, which are affected by 3.3V_EN. Can you see why /WDO doesn't hold for nRST in this situation now with Power rail turn off?

When /MR asserts, /RESET asserts as well.  When /MR de-asserts, /RESET remains low during the fixed reset delay time of tRST and then de-asserts.  With this in mind, /WDO should be in a high-impedance state when /MR asserts.  See below:

Base from your schematic and the scope photo, /WDO can only go low if WDI goes low and stays low for a period of tWD.  Again, looking at the scope photo, all the signals are going low including SET1.  If SET1 = 0, the watchdog timer for the TPS3851 is disabled causing /WDO to become high-impedance, which is seen in the scope photo.  Therefore, /WDO will not stay low for nRST time period.

2. 2.2uF Cap is connected to /MR by Line-to-GND.
If this value is reduced to 1uF, the /WDO Low assert time decreases, but if this value is increased to 4.7uF or more, the following abnormal behavior occurs. There seems to be a problem with timing, In conclusion, the system does not reboot even after a time out occur. Timing seems to have a problem, can you check it once?

Without seeing a scope photo of /MR with a 4.7uF, I can only make an assumption that the /MR voltage is not going low enough to meet VIL spec, which is 0.25V.  The time constant on /MR with a 4.7uF capacitor and a 10Kohm resistor is 47ms.  Please check the /MR voltage with the 4.7uF to see if /MR is actual meeting the VIL spec.

Ben

Dear Ben,

Hi I'm Jieun Hong who is colleague with Siyoon

I have additional questions in the above mentioned.

Accordinig to Siyoon,

2.2uF Cap is connected to /MR by Line-to-GND.

My question is

If this value(2.2uF) is increased to 4.7uF or more, the following abnormal behavior occurs.

After watchdog timing, SET1 pin does not go high, so it cannot be rebooted after a time out occur.

I think it's because of time constant on the MR side.

Please let me know the two things.

1) Why it cannot be rebooted if capacitance on MR is increased. Is there a correlation between MR and SET1?

2) What is the stable time constant value where SET1 pin can be high.(I can not find on datasheet)

Thank you so much for your answer.

Hi Ji Eun Hong,

Please see my answers in green:

1) Why it cannot be rebooted if capacitance on MR is increased. Is there a correlation between MR and SET1?

Placing too much capacitance on MR can cause /RESET to not assert.  In the previous diagrams that were provided by Si Yoon, the MR voltage did not go low enough to initiate a proper reset for the given time.  There is no correlation between MR and SET1.  SET1 determines whether you want to have the watchdog timer operating or not operating.

The MR pin is a logic input pin and therefore is a threshold driven input.   

2) What is the stable time constant value where SET1 pin can be high.(I can not find on datasheet)

SET1 is a logic input where VIH = 0.8V and just like the MR pin, it is a threshold driven input.      

Ben

Thank you very much for response.

I need more detailed answer.

1) I wonder the reason why "Placing too much capacitance on MR can cause /RESET to not assert."

(In the picture below, if the MR goes low, the RESET becomes low even though MR capacitance is 4.7uF(much capacitance))

As you can see this diagram, I just change the MR capacitance 2.2uF to 4.7uF. Then SET1 pin cannot go high, so it cannot be rebooted (abnormally driven)

2) You said there is no correlation between MR and SET1 pin, but why can' t SET1 pin go high?

I have additional questions.

I understand that RESET becomes low when MR is low.

3) But why does SET1 also become low too? Is it operated by the watchdog internal IC?

Thank you for replying

Hi Ji Eun Hong,

A1.  Looking at the scope photo, both /MR and /RESET appears to go down because the rail voltage that is connected to these two pins seems to be turned off.  I would expect the two signals to look more like the WDO signal where the edges are sharp and the voltage is 0V.  Both /MR and /RESET do not go to 0V.  Can I ask why SET1 is also going low?  Again, looking at the scope photo, it appears that the power rail is turned off and /MR, /RESET/ and SET1 goes low as the result of the power rail going low.  

A2.  SET1 is a logic pin that is driven externally.  Is SET1 pin connected to VDD? 

A3.  Again, SET1 must be tied either to VDD or GND.

Ben

Thanks for replying!

SET1 pin is connected to GND by cap and resistor(resistor and capacitor are connected in parallel)

It isn't tied to VDD. Is it the reason SET1 pin goes low when both /MR and /RESET go down?

Jieun

Hi Jieun,

Are you disabling the watchdog timer?  I am confused, in the scope photo it showed SET1 = 3.3V.  Anyway, see below picture regarding SET1.  Remember, SET1 is an input pin.

Ben  

Hi Ben

I'm trying to make sure the watch dog is working well, so I'm going to make MR signal to be asserted and check if the reboot works well.

But if the MR cap is too big, the SET1 does not go high, so it cannot be rebooted.

Jieun

Hi Jieun,

Please tie the SET1 pin to either VDD or GND.  It should not be floating.

Ben

Hi Ben,

I have already tied the SET1 pin to GND...

Thanks for your advice.

Jieun

Hi Jieun,

Is SET1 pin ALWAYS tied to GND via resistor?  

Ben

Hi Ben,

Yes!

Jieun

Hi Jieun,

Are you wanting to disable the watchdog timer?

Ben

Hi Ben,

No, I just assert /MR signal to make a watchdog timeout occurs.

Jieun

Hi Jieun,

I am not sure that makes sense.  If /MR is asserted, the /RESET signal will become asserted and /WDO will be high-impedance.  

Ben

Hi Ben,

Yes, I confirmed that happening.

But SET1 pin also goes low. So the watchdog IC is not rebooted.

Jieun

Hi Ben,

I have additional questions,

As the datasheet, /RESET remains low for tRST after /MR is high.

But, is there any case where /RESET is high before tRST?

Jieun