TPS65186: TPS65186 VN not regulated

Kangwoo Cheon

Part Number: TPS65186
Other Parts Discussed in Thread: TPS65185

Hello, I have made a board that uses TPS65186. I can read & write the register via i2c protocol, and I can activate it by ENABLE register(I tried PWRUP pin also).

but all power rail not regulated except 3v3(enable register becomes 0x20). and VN_UV interrupt flag is asserted

I have been checked VN & VN_SW. VN_SW generates 1MHz PWM for 100ms. VN generator -4V (not -16V) for 100ms. after that it suspended.

What could be cause??

VN voltage

VN_SW PWM Signal

BLUE: VN_SW

RED: VN

over 3 years ago

0 Gerard Copeland over 3 years ago

TI__Genius 10380 points

Hi,

Can you please share your schematic to help debug?

If this is IP I can send you a friend request so that you can share over private message. Please let me know.

Thanks,

Gerard

0 Kangwoo Cheon over 3 years ago in reply to Gerard Copeland

Prodigy 30 points

This is my schematic

and This is my PCB design : I know I didn't follow the layout guidelines (no via on inductor trace, routed away feedback traces, ...) but shouldn't is still work?

0 Gerard Copeland over 3 years ago in reply to Kangwoo Cheon

TI__Genius 10380 points

Hi,

I don't see any issues with the schematic. However, the inverting buck-boost converter layout could be improved.

Component placement for VN should be prioritized. Excessive PCB parasitics between components can result in poor converter performance.

The input capacitor (C22) placement is the most important.
A short, wide trace should be used to connect the SW node to the inductor.
Short, wide traces should be used to connect the components (L9, D2, C24).
For more details, see this blog post: https://e2e.ti.com/blogs_/b/powerhouse/archive/2016/09/28/laying-out-an-inverting-buck-boost-converter-for-success

You can refer to the TPS65185 EVM layout for a tight placement example: https://www.ti.com/lit/ug/slvu548a/slvu548a.pdf

Please note the the wording of the datasheet guidelines - each uses the word "must". If the application layout deviates from these guidelines, the correct operation of the device cannot be guaranteed. TI has only tested and characterized the device with layouts that follow these guidelines.

Thanks,

Gerard

0 Kangwoo Cheon over 3 years ago in reply to Gerard Copeland

Prodigy 30 points

Hi.

Thanks for your advice.

I've already closed this issue, but could you look at my new pcb layout?

Thanks advance.

0 Gerard Copeland over 3 years ago in reply to Kangwoo Cheon

TI__Genius 10380 points

Hi,

Overall the placement of the switching converters looks better. Some additional comments:

If you rotate L8, you may be able to move the boost components closer.
Please add a ground pour covering this layer.
If possible, make the next internal layer an unbroken ground plane. Traces can be routed on the third and bottom layers.
For power components that connect to ground (input caps, output caps, buck-boost inductor), place multiple vias near the ground pad to create a low impedance path to the internal ground plane. The components for both switching converters (C21, C22, C23, L9) should have a lot more ground vias near them.
Connect the other VN inputs (VEE_IN, VNEG_IN) with vias and traces back to the VN output (D2 and C24 connection point). This will ensure noise is decoupled by the input capacitors (C32 and C39) before reaching the pin. Figure 33 in the datasheet shows how this is done on the EVM.

Thanks,

Gerard

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TPS65186: TPS65186 VN not regulated