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TPS56637: Boot strap cap value range

Takashi Onawa
Genius 13200 points
Part Number: TPS56637

Hi Team,

My customer wants to know the lower limit of capacity to which the FET can be turned on even if the DC bias reduce the capacity.
Could you tell me how much effective value is needed for safety?

Also, I'd like to know the upper limit value because too much capacity may cause problems. If possible, please let me know the gate input capacitance of the TPS56637's high-side FET (Ciss).

Regards,

Takashi Onawaw

  • 0
    TI__Expert 7500 points

    Hi Takashi-san,

    Sorry. For this topic, we don't have upper or lower limit value of BOOT cap. We may also can't provide Ciss value which is TI confidential.

    For BOOT cap, recommend to follow TI datasheet and EVM user guide. We did lots of validation with recommended value.

    Thanks,

    Lishuang 

  • 0 in reply to Lishuang Zhao
    TI__Genius 13200 points

    Hi Lishuang-san,

    Thanks for your prompt repose on this.

    OK, I understood that we can not provide such the process information on the internal FET.

    Regarding the Datasheet recommendation. Datasheet says as below but there is no description about effective value considering DC biasing. 

    I understand that it is difficult to mention in detail, but can we get some more detailed comments about the lower limit?

    A 0.1-µF ceramic capacitor(C4) must be connected between the BOOT to SW pin for proper operation. TI recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V or higher voltage rating.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 14455 points

    Hi Onawa-san

        Commonly available 0.1uF with 10V rating should be sufficient. Why is the customer asking for this min-max range?

    Regards,

    Gerold

  • 0 in reply to Gerold Dhanabalan - Online Design Tools
    TI__Genius 13200 points

    Hi Gerold-san,

    Recently, ceramic cap is getting smaller due to suppliers strategy and effective value is also getting smaller at same voltage level due to the size down. 

    Since the DC bias characteristics are also related to the size of the capacitor, they cannot review the design details unless you specify the effective capacitance range.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Expert 7500 points

    Hi Takashi-san,

    Regarding the Datasheet recommendation,

    "A 0.1-µF ceramic capacitor(C4) must be connected between the BOOT to SW pin for proper operation. TI recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V or higher voltage rating."

    I checked two capacitors, one is GRM033R61A104KE15, the other is GRM033C81A104KE14. Both of them are X5R, 10VDC, 0603. The effective cap under 5V DC bias is about 50nF.  So based on this recommendation, the lower effective value should be no lower than 50nF. But this is only the calculated value, not the theoretically guaranteed value.

    Thanks,

    Lishuang

  • 0 in reply to Lishuang Zhao
    TI__Genius 13200 points

    Hi Lishuang-san,

    Thanks for your prompt response on this.

    OK, I will try to close this by the information ; 0.1uF - 50% should be OK because we check that on our EVM.

    Regards,

    Takashi Onawa