Hi, TI expert.
The customer has an inquiry about UVLO operation of LM5119.
- Condition : When forced UVLO off, UVLO off after 321ms Delay by external circuit.
- Questions)
Low Side FET operates intermittently under the condition that UVLO Level is not dropped from 1.2V to 0.4V.
(1CH: Input, 2CH: Output, 3CH: IC UVLO, 4CH: Low Side Gate)
Under the above conditions, UVLO Pin voltage is applied, and it is in Open Loop with Load S/W Off.
It makes sense if the Low Side Gate waveform is maintained or does not appear at all, but the waveform appears like a protection operation.
I wonder why. Is there a specific protection circuit for this?
In addition, there is a schematic with LM5119 applied.
However, because the customer does not want the schematic to be disclosed, please provide your e-mail address. I will send you the schematic.
Please check and answer.
Thank you.
