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Original question:

TLC6C5912-Q1: Any pins pulled up/down internally

TLC6C5912-Q1: SO output circuit and input pin circuits (PU/PD?)

Matthew Pate
Prodigy 20 points
Part Number: TLC6C5912-Q1

Hi,

Please can you confirm: What will be the state of SO output pin in case of loss of power? Will it be FLOATING or are there any internal circuits / pull devices that will pull the output to GND?

My assumption is that this is a push-pull output with no internal pull circuits so that in case of loss of power, nether high-side nor low-side of the push-pull stage can be switched on, so therefore the output pin will be FLOATING - is this correct?

Also, from other answered forum posts, it seems that NONE of the input pins (G / SRCK / RCK / CLR / SER IN) have any internal Pull-up or pull-down devices - is this correct for ALL inputs?

Therefore if two devices are daisy-chained with no external pull-up/down devices connected, and the first one loses power, then the serial data output line from the first one (serial input to the second) will be FLOATING? - is this correct?

Thank you

  • 0
    TI__Genius 15776 points

    You can reference this block diagram:

  • 0 in reply to Frank Qiu
    Prodigy 20 points

    Thank you, I have already seen the block diagram in the datasheet, but block diagrams do not necessarily always show all details of electrical characteristics including functional ones such as pull-up/ pull-down. I have known for these to be omitted from datasheets before, and there is no specific mention elsewhere in the datasheet, hence the question. My assumption would be there are no pull-up/pull-down devices anywhere, but it would be nice if TI could confirm my specific questions above, since assumptions by definition are not always correct.

  • 0 in reply to Matthew Pate
    TI__Genius 15776 points

    1) I can't offer the detail of internal circuit because of the company policy;

    2) I still don't get what's the purpose of your "assumption", if you check the block diagram more cautious you can find the output is only a NMOS and called "current sink"

    3) If the Iq is your concern, i suggest you to use a high side switch before the power stage to achieve the 0 iq