• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 271 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS54326: How to estimate this power is stable or not, through switching jitter?

MINGKUN HE
Prodigy 60 points
Part Number: TPS54326

In normal PWM mode control regulator, if its phase jitter is less than 10% of its pulse width, it might stable.

In TPS54326 design, how to estimate it? Less than 10% of its period?

  • 0
    TI__Expert 7430 points

    Hi MINGKUN

    Our America team will give you feedback soon.

    BR

    Ruby

  • 0
    TI__Expert 7500 points

    Hi Mingkun,

    For our DCAP/2/3 part,  the on-time is well-controlled by internal circuitry, on-time jitter is a negligible effect for this type of control. However, the off-time (time between tON pulses) is generated by comparing the output voltage ripple to the voltage reference. In most applications, it is desirable to minimize the amplitude of the output voltage ripple, so it can be seen that the decision point happens on a much smaller scale than that of voltage or current mode control. 

    The switching jitter in DCAP designs remains generally larger compared to linear schemes like voltage and current mode control.  

    But honestly, for DCAP mode, we don't have an exact percentage of jitter that can promise system stable. 

    Thanks,

    Lishuang