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UCD90120A: Wrong alter happened in MON

Part Number: UCD90120A
Other Parts Discussed in Thread: UCD90SEQ64EVM-650,

Hi team,

Customer use our EVM board to do evaluation but they get some problem here.

Need team's help to solve this problem. see attached file for their programing setting.

Besides, they also want to know below questions.


EVM Board: TI HPA650 REV. B, UCD90SEQ64EVM-650, with UCD90120A chip inside.EVM Programming.pdf
(1) the relationship between Margin limit and FPWM function
(2) and how to implement the FPWM function and measure it for urgent

  • Hello

    First, i would recommend the attached quick guide for customer to understand some basic usages.

    UCD90xxx 简易使用手冊.pptx

    Margining is to design for the 4-corner test to ensure that the power supply can reliably work under Min/Max voltage range. You need to have a special circuit in place to use this function.  Please refer the below two application notes and design spreadsheet. 


    Let me know exactly what they want to do so that i can better assist. 



  • Hello Yihe,

    I am the customer for this request.

    Thank for you helps of many documents. Really helpful, especially PPT.

    Actually, the sequence, enable behavior and margin conditions is easy to implement.

    And I also set the duty and frequency by design guide and excel before asked this question.

    --------------------------------------------------------------------------------------- question line --------------------------------------------------------------------------------------------------

    For now, I use electric load to simulate the criteria for margin test.

    Typically, Vout = 1.8V, Margin High(MH) = 1.836V, Margin Low(ML) = 1.764V,

    I have set Vout scal, too.

    Margin set to "Low", "Operation cmd" set on, use electric load to make voltage under margin low condition continuously.

    UVF signal is alert (actually once CTRL pull high, this fault alert happend),

    but I don't see the FPWM LED lighting with specific frequency and voltage back to margin criteria.

    I also found once CTRL pull high, the FPWM lights with short period(within a second),

    the voltage go back to margin criteria randomly not every time, is these behavior correct or what I missing???

  • Hi

    For the margining test, there is no need to use any electric load. It is done between UCD and the downstream power supply. 

    When the margining is turn on, UCD will change the duty cycle of the PWM to impact the feedback voltage of the power supply which adjust the output voltage accordingly to do margin HIGH/LOW test. There is no need to have the load to simulate.  What is load for here?

    In order to do the margining, there are two condition to meet:

    1. the rail is physical ON(it means that the condition of ON/OFF_CONFIG is met to turn on the rail, the rail's sequencing on dependencies are met)

    2. the rail's voltage is above its POWER_GOOD threshold 

    You have to solve the UV fault issue first. There is about 1% differences between the Margining and UV threshold. you may try to increase the gap.



  • Hello Yihe,

    The electric load is my misunderstanding for margin corner test. Drop it now, thanks.

    For now, I use a 1.8V power chip connecting to UCD EVM device

    Power chip Vout -> MON of UCD device

    Power chip VFB -> FPWM pin with T circuit referred to TI design guide

    Power chip GND -> UCD device GND


    (1) the power chip don't support SW feature, is it OK?

    (2) All connection realized by Dupont Line, suitable?

    From monitor display of Fusion GUI, it always shows 1.799~1.805V information legally, I don't understand why the UVF happened!!!

    And I set the margin low value is 1.764V, but the value from 1.817V to 1.825 as result.

    1. the rail is physical ON(it means that the condition of ON/OFF_CONFIG is met to turn on the rail, the rail's sequencing on dependencies are met)

    -> What's that mean? If I set 7 rail on EVM board, I need to prepare 7 downstream power supply to fulfill this conditions first, then verify margin? (PS: I don't set any dependencies for now)

    2. the rail's voltage is above its POWER_GOOD threshold

    -> If fail, UVF happened??? or what kind of error message occurred?

    By the way,

    The FPWM have HW rule of frequency FPWM1 = FPWM2; FPWM3 = FPWM4...

    If the optimal frequency calculated by excel don't equal with each other, what's your suggestions?


  • Hello


    1.  UCD is a monitor device and it does not support SW mode.

    2. the EVM was designed long time ago and it does not have the recommend thing to improve ADC accuracy, such as decoupling cap on the MON pins. 4.99ohm resistor between V33A and V33D. all these are critical for the ADC accuracy which impact the margining as well.  The GUI has a 500ms refresh rate so it may not display all the voltages. 

    Device reports UV fault only if:

    1. the rail is physical on

    2. the rail has been above power good threshold and then fall below the UV thresholds.

    Please use the lower frequency for the case if one pair FPWM has different frequency.



  • Yihe,

    It should be solved so far. If customer has further question I will ask again.


  • Hello Paul,

    Response as below

    1.  UCD is a monitor device and it does not support SW mode.

    -> The power chip means the downstream power supply not UCD device. I want to know if the downstream power supply must to choose for supporting SW mode or not. This issue may affect the downstream power supply choice.

    So my experimental environment is suitable? or something need to modify, could you give me some feedback?

    For rail is physical on issue: After "Control Lines(USB)" pull high and match power good conditions, then I turn on the margining.

    is this procedure OK???

    For now, the margin high and margin low function could be realized, but the output value doesn't match what I set

    Tuning Duty cycle and frequency no work. Is it normal???

    Actually still many questions need to clarify and improve. Thanks.

  • Hello

    1. The downstream power must support adjusting FB voltage to change output voltage. 

    yes, you have to enable the margin after rail is on and reaches POWER_GOOD thresholds.

    you may have to adjust R3 and R4 resistor to change Margin HIGH/LOW output accordingly.



  • Hello Yihe,

    Thank for your feedback.

    So tuning the duty and frequency doesn't work, right?

    I have adjusted the margin range by tuning R3 and R4 before asking this question, more solution?

    Addition, could I have a call or personal communication with you? Thanks.

  • Hello

    The margin HIGH/LOW threshold is determined by the R3/R4 and R1. Please refer section 2.1 of

    Reducing R3 and R4 shall help.



  • Hi, Yihe

    Thank for your comments.

    I would study it for detail, thanks.

    Dear Paul,

    This discussion could be close for now, thanks.

  • Hi 

    Thank you for the reply. Please let's know if any further help is needed.