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Original question:

TLC5958: Microcontroller for TLC5958.

TLC5958: TLC 6946 fpga demo code for multiplexed led matrix

Kishore B2
Prodigy 75 points
Part Number: TLC5958
Other Parts Discussed in Thread: TLC6946

Dear Swan,

We tried to implement driver for tlc6946 in fpga and microcontroller also. 

But we could not succeed. The board we designed is not responding to any changes Function control registers e.g brightness control, number of lines selection...etc. 

Do you have fpga demo code for TLC6946 for multiplexed 16x32 led matrix?

If you don't have demo code, please assign FAE to support us.

Regards,

Kishore

  • 0
    TI__Genius 12915 points

    Hi Kishore,

    We do have no FPGA code, would you mind to share your code?

    And we should know your company information before find a FAE to support you.

  • 0 in reply to Hardy Wu
    Prodigy 75 points

    Dear Hardy Wu,

    I shared the folder which contain FPGA and micro controller code.

    We took FPGA FC registers screen shot of DSO and its information also present in the folder.

    1.We are writing FC1 to FC4 registers modified from defaults are

    a) 32 scan lines,

    b) Full brightness

    2. We are switching line once each  sub period, and in each subperiod we are sending 310 GCLKs

  • 0 in reply to Kishore B2
    TI__Genius 12915 points

    Hi Kishore,

    Could you help to send a mail to shawn-ding@ti.com, which would let us know your contact method. We would continually support through mails.

  • 0 in reply to Hardy Wu
    Prodigy 75 points

    Since we did not get reply, I am posting my question here.

    Dear Shawn,
    Since we are new to fpga programming we are trying to make the TLC6946 working with microcontroller,
    once it is completed we will use fpga . As per the datasheet we are writing default FC registers,their waveform have been attached bellow.
    only change is in FC3 register, we made the number of scan lines 32.
    We are able to read FC registers from SOUT pin.
       
    As per the suggestion you have given we are following Step1 to Step7 as it is. In Step8 by default the mode is 8+8 and after calculating the number of gclk acording to datasheet we are getting 310 GCLK and we are sending as follows:

    <<code is removed as it is not informative>>

    we are filling complete buffer with full brightness.
    still we are not able to get the desired output.
    Please suggest us whether we are doing right or not.
  • 0 in reply to Kishore B2
    TI__Expert 3190 points

    Hi Kishore,

    It is hard to figure out the issue from the code.

    so you mean you can conform that the FC registers have been written and read without problem, right?

    have you sent the VSYNC command after finish the data sending?

  • 0 in reply to Shawn Ding
    Prodigy 75 points

    Hi Shawn,

    We cross check fc register read and write. We could able to read and write fc registers property.

    We are sending vsync also.

    We are using 8+8 mode 16x32 matrix with 1/32 multiplexing

    310 gclks not devidable by 32 rows, We have unclear point as below.

    1. how to send 310 gclks in sub period. 

    2. When to switch line. 

    3. How much delay needed.

    Please clarify.

  • 0 in reply to Kishore B2
    TI__Genius 15776 points

    Hi Kishore, it's hard for our expert to check the whole code please answer Shawn's question and offer his step to debug by yourself.

  • 0 in reply to Frank Qiu
    Prodigy 75 points

    This Kind of answer does not help. you are very late in giving replys. we have unclear points in the specification.

    We are using 8+8 mode 16x32 matrix with 1/32 multiplexing

    As per design example mentioned in the spec, 310 gclks are required.

    310 gclks not devidable by 32 rows,

    1. how to send 310 gclks in sub period?

    2. When to switch line ?

    3. How much delay needed ?

    Please clarify.

  • 0 in reply to Kishore B2
    TI__Genius 15776 points

    Hi Shawn, could you help in this case.

  • 0 in reply to Kishore B2
    TI__Expert 3190 points

    Hi Kishore,

    we could not suggest you how to send 310 GCLK from MCU/FPGA, we just can tell you if you want to operate this device, you need to follow the protocol of this device, that means you need to program the timing and sequence by following the technical reference manual.

    Step1:  FC: Keep LAT high with 15 SCLK rising edge, then LOW

    Step2: FC1: Keep LAT high with 5 SCLK rising edge, then LOW; meanwhile, sending data on SIN wire

    Step3: FC2: Keep LAT high with 7 SCLK rising edge, then LOW; meanwhile, sending data on SIN wire

    Step4: FC3: Keep LAT high with 9 SCLK rising edge, then LOW; meanwhile, sending data on SIN wire

    Step5: FC4: Keep LAT high with 11 SCLK rising edge, then LOW; meanwhile, sending data on SIN wire

     

    Step6: Write GS: Keep LAT high with last 1 SCLK rising edge, then LOW; meanwhile, sending data on SIN wire

    Step7: VSYNC:  Keep LAT high with 3 SCLK rising edge, then LOW

     

    Step8: enable the Line switch, then send 310 GCLKs,

    Step9: disable the current line switch, then enable the next line switch, then send 310 GCLKs

    Step10: repeat step9, until the end of the display

     

    Step11: Wait for current frame displayed (might be 60Hz..)

    Step12: Go to step6

  • 0 in reply to Shawn Ding
    Prodigy 75 points

    Thank you for your information.

    In the spec we are confused with line switching within sub period mentioned in

    Figure 3-7. TLC6946 Multiplexed 8+8 Mode of ES PWM (32-Multiplexing) in the spec SLVUBF4A.

    As per the procedure given by you, it should be one line switch for one period.

  • 0 in reply to Kishore B2
    TI__Genius 15776 points

    Please follow Shawn's step first.