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BQ24765: SMBUS access timing on reading Register

user4030081
Prodigy 100 points
Part Number: BQ24765

Hi dear supporting team,

When reading the registers of Battery Charger SMBus Registers, I think that it is done as follows.

(1)Start condition
(2)Send SLAVE ADDRESS (0b0001001) +0b0 in sync with CLK from the master device
(3)ACK returned from BQ24765 during ninth clock
(4)Send COMMAND BYTE(8bit) from master device
(5)ACK returned from BQ24765 during ninth clock
(6)Send SLAVE ADDRESS (0b0001001) +0b1 in sync with CLK from the master device
(7)ACK returned from BQ24765 during ninth clock
(8)LOW BYTE DATA are output from BQ24765 in synchronization with CLK
(9)ACK returned from master device during ninth clock
(10)HIGH BYTE DATA are output from BQ24765 in synchronization with CLK
(11)NACK returned from master device during ninth clock
(12)Stop condition

Do I need wait time between (7) and (8) ?

  • 0
    TI__Genius 11850 points

    Hi,

     

    No, you do not need to add an extra wait time between steps 7) and 8). After the ACK bit is clocked into the master, data transmission can begin on the next clock cycle when SCL goes high. This is shown by "F" and "G" in Figure 16.

     

     

    Also, for a register read, don't forget about the 2nd start condition highlighted below. This should come in between steps 5) and 6) in your procedure.

     

     

    Best regards,

    Angelo