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UCC21750-Q1: UCC21750 power supply fault problem

Gowthameswrao Motepalli
Prodigy 30 points
Part Number: UCC21750-Q1

We are using this ic for gate driving of SIC mosfet.But suddenly after some times Power supply fault is appear. we are tied the fault and RDY pins are together.But we are not usnig AIN and APWM pins .SO, please give the suggestion for this problem. If AIN and APWM pins are not using then what will do of these pins , is it floating  or any connections to be made.

  • 0
    Prodigy 30 points

    We arer using the 40Khz frequency and measure the 15 V for gate drive side and 5V for PWM input we measure the 15V supply at the time of tripping and no dip on 15V but 300mV pk to pk ripple voltage appear when switching of mosfet and 5V should be 4.93 V.

  • 0 in reply to Gowthameswrao Motepalli
    TI__Genius 13650 points

    Hi Gowthameswrao,

    Welcome to E2E!

    If AIN to APWM function is not used connect AIN to COM and leave APWM floating.

    For the reporting issue I have a few questions:

    1. If RDY and FLT are tied together have you done some test that separates the RDY and FLT pins signals to verify that RDY pin is the signal reporting the fault?
      • RDY and FLT are two different mechanisms. It would be good to confirm which open drain output is causing the signal to go low.
    2. Does the fault occur at when running the SiC mosfet at high power levels, or does it always occur even under no loading conditions?
    3. If the FLT occurs only at higher power would you be able to run some tests by increasing the gate resistors to slow down turn on and turn off dv/dt?
      • My first assumption is that the issue might be coming from noise being coupled into the driver from the gate loop. Slowing down the dv/dt would not be the final solution, but it will help us understand the nature of the issue.

    All 4 questions above should help us narrow down on the root cause of this issue. Let me know if there's any questions!

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 30 points

    Hai Andy,

    Thank you for your valuable reply .

    We are not tested  the RDY and FLT pins separately. This fault appear the system running with high power only.

    But the fault is appeared due to RDY only due to it was reset after 500us due to power supply is again good .But if fault will appear with desat then fault is not reset until the next PWM signal rising coming from control card once it will shut down pwm pulses due to fault.

    Best regards

    gowtham

  • 0 in reply to Gowthameswrao Motepalli
    Prodigy 30 points

    Hai Andy ,

    We tied the RST /EN pin was tied to Input PWM pulse.

  • 0 in reply to Gowthameswrao Motepalli
    TI__Genius 13650 points

    Hi Gowthameswrao,

    Your last comments are right non point. The fault not resetting at the next rising edge lets us know that it is in fact the RDY open drain output that is pulling the node low.

    This issue is likely due to significant gate ringing during the switching transient. If possible to verify this I would recommend to monitor OUTL-COM and VEE-COM right at the pins of the gate driver with the smallest probing loop possible. Using the full bandwidth of the probe available and maximum sample size (>1GS/s preferred) we could capture the noise on these pins and apply some of the mitigation methods below:

    1. Increase turn off gate resistance to slow down turn dv/dt.
    2. Increase VDD and VEE bypass capacitors.

    The following methods would require board change:

    1. Reducing the stray inductance in the gate loop.
      • I can help with a schematic and layout review to optimize the gate driver configuration
        • If there's confidentiality issues we can take this conversation into email
    2. Reducing stray inductance in the miller clamp path.
    3. Add a Ferrite bead between gate resistors and switch gate.
    4. Add clamping diodes
      • From OUTH to VDD to mitigate overshoot
      • From OUTL to VEE to mitigate undershoot

    The above methods can help you verify gate ringing is the issue and ways to mitigate it. Do let me know if you would like me to assists with a schematic and layout review so I can send you a friend request through this E2E forum to share my email.

    Best regards,

    Andy Robles