Other Parts Discussed in Thread: TPIC6C596
Hello Team,
can several cascaded TPIC6C596s be replaced by TPIC6C595 in an application which drives relays keeping the same timing?
SRCK is between around 7 MHz.
Thanks and Best Regards,
Hans
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello Frank,
we intended (actually we need) to replace TPIC6C596 with TPIC6C595 in many existing design for reasons of availability. Each SER_OUT is routed to the SER_IN of the next device in the chain, with chain length up to about 30 devices on one board. There are good PWR/GND planes, and adequate clock drivers an termination. However, the '595 datasheet recommends a SER_IN hold time of 20ns after SRCK, while the T_CO of SER_OUT is only 15ns typically. So the typical application circuit would theoretically fail timing. The '596 avoids this issue by delay SER_OUT by 1/2 clock period. I tried it with the '595, it actually works over temperature even with a few ns of timing margin. So is this hold time requirement only meant for widely scattered systems with poor signal integrity? I appreciate your advise.