• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 4 answers
  • Subscribers 63 subscribers
  • Views 221 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LP87702-Q1: watchdog's counter can not be cleared.

YIN CHI HUANG
Prodigy 60 points
Part Number: LP87702-Q1

To TI's team,

Sorry for bother, I have a question concerning watchdog on lp87702-Q1.

First, I wrote 0x01(even 0x02) on register 1Ch bit WD_RESET_CNTR_SEL. I read

current watchdog reset counter which was on register 1Eh bit WD_RESET_

CNTR_STATUS and found the the counter was 1. I wrote 0x01 on bit WD_CLR_

RESET_CNTR to clear the counter. However, the counter was not clear. Therefore, I 

wrote 0x03 on register 1Ch bit WD_RESET_CNTR_SEL and did the same steps above.

The counter was clear, did I misused or there was something wrong? 

Many Thanks,

Eric

  • 0
    TI__Expert 4355 points

    Hi Eric,

    Firstly I would like to know the watchdog window settings used and what are timings for WDI signal provided to the device. Have you measured the WDR pin with an oscilloscope? In other words, is the watchdog reset generated? If the reset is generated it will reset the counter back to zero.

    Writing WD_CLEAR_RESET_CNTR to 1 should clear the counter even if the WD_LOCK is 1. 

    I suspect that the WD input timings may not be correct creating watchdog errors. The WD errors caused by incorrect WDI signal could be increasing the counter faster than you are trying to clear it. Basically the device may be in a watchdog reset loop.

    Best regards,

    Samuli Piispanen

  • 0 in reply to Samuli Piispanen
    Prodigy 60 points

    Hi Piispanen,

    My watchdog settings are WD_LONG_OPEN_TIME = 0x03 (5000ms), WD_CLOSE_TIME = 0x03 (100ms), and WD_OPEN_TIME = 0x03 (600ms) respectively. As for WDI signal, I provided it every 200ms which was checked via oscilloscope. Also, the WDR pin was measured a pulse via oscilloscope when the program went into while(1) intentionally and then reset  happened. According to the situation above, I thought WDI signal was successfully provided, and the watchdog reset was functional when time-out.

    Many thanks,

    Eric  

  • 0 in reply to YIN CHI HUANG
    TI__Expert 4355 points

    Hi Eric,

    The WD_CLOSE_TIME and WD_OPEN_TIME settings are both set via I2C during long open window, right?

    WDR should not pulse if the WDI settings are correct. The device may reset back to the OTP default settings depending on the WD_EN_OTP_READ setting.

    Best regards,

    Samuli Piispaen

  • 0 in reply to Samuli Piispanen
    Prodigy 60 points

    Hi Piispanen,

    All settings were set via I2C and the pmic watchdog worked smoothly. However, the counter was still can not be cleared.

    Many thanks,

    Eric  

  • 0 in reply to YIN CHI HUANG
    TI__Expert 4355 points

    Hi Eric,

    I have observed the same behaviour. Please send me an email and let's continue this discussion via emails.

    Best regards,

    Samuli Piispanen

  • 0 in reply to Samuli Piispanen
    Prodigy 60 points

    Hi Piispanen,

    Thank you for the technical support, I will contact you ASAP!

    Many thanks,

    Eric

  • 0 in reply to YIN CHI HUANG
    TI__Expert 4355 points

    Hi Eric,

    Thank you. I saw your email. Let's continue the discussion through emails.

    Best regards,

    Samuli Piispanen