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Converter Synchronization issue using UC2825A-EP PWM IC.

Daniele Reni
Prodigy 30 points
Other Parts Discussed in Thread: UC2825A-EP, UC2825

I am having problems synchronizing the PWM IC UC2825A-EP to an external 120Khz clock frequency. The problem occurs during high and low temperatures (-40 Deg Cent. and +70 Deg Cent.)

The PWM frequency varies from 105Khz to as much as 118Khz around these temperature ranges. The external RC components are 1% tolerance, I am using an NPO capacitor for the CT, and we also tried using a film capacitor as well. The external components are not the cause of these wide frequency variations. I believe that the frequency variations are due to temperature, for the most part, caused by the PWM IC temperature tolerances.

I am using the recommended External sync circuit found the the UC2825 datasheet.

In the datasheet the UC2825A-EP has listed a tolerance of +/-5% for the Oscillator temperature stability and about +/-6% for the initial oscillator accuracy. When the free running oscillator is set to the recommended frequency of 10% to 15% slower than the sync frequency, the tolerances of the free running oscillator in the UC2825 drift out of the window in which it can be sync.

I called a TI App Engineer and he recommended using a different sync circuit (as shown in a TI technical Paper “Converter Synchronization Provides Design Flexibility” by John Bottrill):

This circuit is specifically designed for PWM ICs with integrated CT caps. However the TI App engineer thought that this would work fine for our application using the UC2825 as well (it does not have the integrated CT cap).

Question 1:         Will this new circuit be able to sync correctly over the UC2825 frequency variations due to temperature and initial tolerances?

Question 2:         What is the min and max frequency tolerance in which this new circuit will still be able to sync to the sync frequency using the UC2825 PWM IC? (Our     current circuit won’t sync well below 10% of the sync frequency).

Question 3:         In the case of this new design example, the CT-Buffer is the signal output that is used to reset the external SR latch. If I use the UC2825, what is the equivalent signal? (I think it is CLK/LEB pin 4).

  • 0
    TI__Mastermind 25130 points

    Daniele,

    It should work with the following in mind.

    With pefect  ideal components you will have a 12.5% variation chip to chip over line and temperature.with fixed Rt of 3.65kohms and a Ct of 1.0 nF. For different frequencies the tolerances will be different. This does not include any variations in the Rt or Ct due to temperature changes.

    Any tolerance variations of either Ct or Rt  will impact the frequency.

    The voltage on pin 3 (Rt) is approximately 3 volts. The current out of pin 3 is mirrored by the current out of pin 6 (Ct) which charges the Ct..

    If you design both converters to run at 400 kHz with .1% Rt and 5%for Ct over temperature and both were allowed to free run you could end up with one converter 18.5% above the desired frequency and the other 18.5% below the desired frequency.

    Decide which is to be the master. Using the Master's CLK/LEB pin create a negative going spike in time with either the leading or trailing edge of CLK/LEB signal.  (leading edge is probable easiest). This will be your SYNC pulse.

    Using the paper you mentioned connect the U1-A to the  CLK/LEB pin of the circuit to be synchronized (the slave).

    You should now be able to follow the paper to get the necessary voltages. Since you want to balance the voltage across the circuit to be balanced about 3 volts you will have to get a 6 volt source instead of a 5 volt  source as shown in Figure 1 of the paper. Choose R5so that with 2 volts across it you get 20% of the current through Rt  at 3 volts.

    Choose R4, R3 and R2 to be small enough that they will  be very small compared to R5. C3 has to be large enough that there is negligible change in voltage with the current through it. C3 and C4 are filter caps. They take the phase difference between the master pulses and the slave pulses and generate a low frequency voltage that will adjust the current from the Rt pin in such a manner as to pull the slave into the same frequency as the master.

    It is basically a voltage controlled phase locked loop.

    Good luck,

    John  

     

     

    .

     

  • 0 in reply to John Bottrill
    Prodigy 30 points

    We simulated your sync circuit with PSpice and initially it was not working right. After some studying we noticed a schematic print error.

    C3 on your schematic is repeated twice.  In our analysis we found that the C3 that is after the buffer and in series with R2 prevents the filtered voltage to vary as a function of the duty cycle.

    We then removed the C3 and R2 components and we also removed the two shotkey diodes as well.

    We also found that the circuit was working much better if the clock sync has a wide duty cycle with a very narrow off time. This allows the SR flip flop to sync to a wider window of frequencies.

    With these changes we were able to get this circuit to work well in PSpice and we are going to bread board it and test it next.

    If possible we would appriciate if we could call you to discuss these design changes more in detail over the phone.

    We appriciate your help and prompt responses.

    Thank you,

    Daniele and Lorin

    cell phone 801 7031615

  • 0 in reply to Daniele Reni
    TI__Mastermind 25130 points

    Daniele,

    You are right there are two C3 capacitors, In the original version the C3 next to R2 was C2. The miss numbering must have occurred between the time it was submitted to the time it was printed.

    C2, R2, D2 and D3  provide a DC isolated square wave with a defined magnitude to the low pass filters. You have to consider what will happen if the sync signal were to disappear. What would that do to the frequency of the slave unit. Without that circuit the converter would swing to either a high or low extreme instead of sitting near its designed mid point.

    Your comment:-

    We also found that the circuit was working much better if the clock sync has a wide duty cycle with a very narrow off time. This allows the SR flip flop to sync to a wider window of frequencies.

    Which is why I wrote -  Using the Master's CLK/LEB pin create a negative going spike in time with either the leading or trailing edge of CLK/LEB signal.  (leading edge is probable easiest). This will be your SYNC pulse.

    Different words to define the same results.

    Regards,

    John