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TPS65381A-Q1: VCORE rail on TMS570LS3137

Siby James
Expert 5140 points
Part Number: TPS65381A-Q1
Other Parts Discussed in Thread: TMS570LS3137, TPS57160-Q1,

Hi,

In the TPS65381A datasheet it looks like VDD1 (linear regulator capable of 1.2V output for the Hercules) uses an external pass FET with no current or temp monitoring. Thus, it looks like we recommend using VDD6 as a current-limited source for VDD1. Because all the LDO rails feed off VDD6, this leaves 600mA guaranteed for VDD1.

The TMS570LS3137 has a max Vcore draw of 700mA during PBIST.

To get around this current limit, it looks like we use the TPS57160-Q1 to supply vcore in TIDA-01537. Is this recommended from a functional safety perspective? All the safety related functionality seems to live on the TPS65381A, which does not supply or monitor VCORE. Can I bypass the VDD1 regulator and instead use VDD1_SENSE to watch the 1.2V output from TPS57160.

  • 0
    TI__Genius 9310 points
    Siby,
    Yes you can. The thermal design considerations when using a 24V input supply is of most concern. The TPS65381A-Q1 includes a pre-regulator from input to 6V and then downstream LDOs with integrated FETs for all regulators except VDD1. VDD1 is used to generate the core voltage and is an LDO controller with external FET, but the sense pin can also be used to monitor the output from a DCDC when thermal and efficiency concerns require such an approach. In some cases it may be necessary to provide a pre-regulation from 24V to an intermediate voltage such as 8 to 12V to spread the power dissipation.
  • 0 in reply to Gordon Varney
    TI__Mastermind 20580 points
    Hi Siby,

    I have also just added an FAQ to the TPS65381A-Q1 on the E2E forum helping add additional clarity and another example TI Design where the VDD1_SENSE pin is used to monitor the output of a DCDC used to power the 1.25V core rail of a TMS570 or Hercules MCU. The functional safety discussions can get very detailed and really depend on the end customer system requirements and safety goals which will driver their hardware safety requirements which put the actual requirements on the TPS65381A-Q1 and other devices used in the system. These approaches help the customers solve various aspects of potential requirements they may have.

    This FAQ may be found at e2e.ti.com/.../2759340
  • 0 in reply to Scott Monroe
    TI__Expert 5140 points
    Hi All,

    Thanks for the great responses + collateral. This is very useful. All in all, to clarify, we can leave the VDD1 gate drive pin disconnected when using an external DC/DC? It seems that we just need to make sure VDD1 isn't enabled.
  • 0 in reply to Siby James
    TI__Genius 9310 points
    Siby,


    If the VDD1 regulator is not used, leave the VDD1_G and VDD1_SENSE pins open. An internal pullup device on the VDD1_SENSE pin detects the open connection and pulls up the VDD1_SENSE pin. This forces the regulation loop to bring the VDD1_G output down. This mechanism also masks the VDD1_OV flag in VMON_STAT_2 register and therefore the ENDRV pin action from a VDD1 overvoltage (OV) condition is also masked. These actions are equivalent to clearing the NMASK_VDD1_UV_OV bit in the DEV_CFG1 register to 0. This internal pullup device on the VDD1_SENSE pin also prevents a real VDD1 overvoltage on the MCU core supply in case of an open connection to the VDD1_SENSE pin, as it brings the VDD1_G pin down. Therefore, in this situation, the VDD1 output voltage is 0 V. By default, VDD1 monitoring is disabled. If the VDD1 pin is used in the application, TI recommends to set the NMASK_VDD1_UV_OV bit in the DEV_CFG1 register to 1 when the device is in the DIAGNOSTIC state. This setting enables driving and extending the reset to the external MCU when a VDD1 undervoltage event is detected.

    The VDD1_SENSE pin may be used to monitor the output from the other regulator and the VDD1_G (gate drive pin may be left floating). The VDD1_UV and OV flags and device reactions will occur the same as if the VDD1 LDO controller is being used with an the external FET to generate the output voltage for the VDD1 regulation. The target sense voltage for VDD1_SENSE is 0.8V. The software must ensure NMASK_VDD1_UV_OV is set to 1 while the TPS65381A-Q1 is in DIAGNOSTIC state to enable the UV and OV monitoring function so a detected VDD1 UV event will cause the TPS65381A-Q1 to transition to its RESET state, pulling the NRES pin and thus the MCU reset bus low and causing ENDRV pin (safing output) to also be driven low during a UV or OV event on the VDD1_SENSE pin. Please note the resistor tolerance used for the resistor divider for the voltage monitoring will impact the UV and OV monitoring tolerance.

    Simply put, If the VDD1_G pin is left floating VDD1 is disabled, and you have to set NMASK_VDD1_UV_OV to 1 while the TPS65381A-Q1 is in DIAGNOSTIC state to use the monitor functions. You do not have to make sure VDD1 isn't enabled or disabled.