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Part Number: CSD19532KTT
Customer would like to confirm below two things. They would like to use CSD19532KTT but found this will be broken by lifetime test. They would like to solve this break and has below questions.
1. CSD19532KTT is being used for motor application. And the drain-source voltage applied to this FET can exceed 100V during 3usec in a 50usec period. They would like to confirm whether this short time violation of the absolute maxim ratings are acceptable. Could you give any comments on this?
2. Customer would like to understand the definition of power dissipation of absolute maximum voltage. How should they understand this?
They are thinking like below.
Power dissipation should not exceed this value even for just a very short time.
This value is the power dissipation when the junction temperature will exceed a certain temperature at 25C ambient temperature. So this means it may be OK to exceed this power dissipation if the junction temperature doesn't exceed a certain temperature. They think that heat sink may help if the latter one is correct.
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In reply to Chris Bull:
In reply to Noriyuki Takahashi:
Yes there are a few potential ways to reduce various ringing and even EMI.
The schematic below shows a full bridge topology (but could be applied to 3 phase) used to drive a DC Brushed motor.
Vds across each FET is controlled by an RCD clamp to reduce the drain to source ringing. Resistor 27Ohm, Cap 0.1uF, Diode 1N4148 are used in this example.
The motor winding has an RC snubber across it to reduce EMI. 56 Ohm resistor and 0.1uF cap in this example.
In cases where gate voltage exceeds the Vgs rating of the FET, a zener diode is used to protect the gate of the FET by clamping it to the Zener voltage. MM3Z15VT1G zener used in this example.
please find schematic here
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