TL5209: Output capacitor

Hi Gerard,

Thank you for the response.

Let me explain a little bit about the context of the question.

I am trying to debug a problem a with a design that closely follows one of the designs I listed, with a 10uF ceramic capacitor. The cap there has an ESR around 1 - 1.5 ohm or so in the frequencies of interest. The design is actually well-vetted at temperature extremes and under load and has been in production for a couple of years without any issues, but a recent manufactured batch has shown problems at low temperatures under 0C, while working fine at higher temperatures.

Now, there has been a cross of the original output capacitor in this batch, and the new cap may be somewhat lower ESR, seems to be around 0.4 - 1 ohm. So, the first thought was whether the lower ESR was introducing instability, which is why I wanted to ask about the comment in the datasheet of "too low an ESR may cause oscillations" and what would be considered "too low" in this case.

I should point out that a couple of pieces of evidence actually point away from loop compensation issues:

a) the problem happens at low temperature, but per the cap manufacturer data, ESR actually increases with decreasing temperature, so what is seen is actually the exact opposite of what should be happening if there was loop instability due to low ESR

b) the problem is not quite ringing on a load transient, but rather a large (1.5V or so) low-frequency (8 - 10 kHZ) oscillation in the output voltage under pretty steady load of about 60mA - this doesn't seem to be a transient ringing/settling sort of issue.

I have attached a trace of what happens - the yellow trace shows the output rail behavior.

All of which leads me to think that it is not a control loop stability issue with low ESR, but rather the capacitor failing at low temperature in some way.

However, since the datasheet mentions 1 ohm and also that low ESR can cause issues, I just wanted to check if and at what values of ESR one might expect to see issues like this, what ESR would be considered too low. So, appreciate if you can comment or advise.

Thanks,

Best regards,

Anand.

Hi Anand,

You mentioned this behavior occurs with a steady load of 60 mA. I do have a few questions:

What are the other 3 signals in the scope shot shown above?

Would you be able to provide a scope shot of a functional board under the same test?

Is the output capacitor the only component related to the LDO that was changed for this batch of failing PCBs?

I agree that it does seem like a component issue rather than a stability issue. However, applying a worst-case load transient test from 1 mA to 500 mA to 1 mA at 1 A/us would still be best way to determine if the device is unstable with the new output capacitor at low temperatures. The typical transient response to this test is shown in Figure 24 of the datasheet:

Thanks,

Gerard

Hi Gerard,

Thanks for the response. Some more background: The regulator in question is feeding a single eMMC flash chip which is the main storage element for this device. It is feeding nothing else at all. The problem started with observed flash corruptions, so we were probing the MMC bus for issues initially, not suspecting the power supply.

So, the scope shot is when a heavy flash write is being performed and the other signals are from the high-speed MMC interface. The purple is a 48 MHz bus clock, the green one in the command line and the blue one is the data bit 0 line. They are not too relevant except to note that when the dense clock signal starts, that's when the bus transfer of data and flash write is happening, with correspondingly about 60 mA load.

And yes, other than being manufactured at a different time and thus using components with different date codes, no other component other than the output cap was changed - same host processor (TI AM3352), same eMMC flash etc.

The functional board's trace is below. Quite boring, and nothing at all happening. Please note that here we didn't probe the MMC bus lines - this being a high-speed bus, the rig to probe the lines inside the temperature chamber was a bit involved and we didn't do it here, but the same heavy flash write is assuredly being performed when the trace was captured. In other words, the ~60 mA load is present throughout this capture.

I have now also replaced that single output capacitor on a board with the problem with a new 10 uF capacitor and confirmed that this eliminates the problem completely and produces the same trace as below. The problem is conclusively now pinned to the output capacitor.

I will try and do the maximum load step transient response capture later today or tomorrow.

Thanks,

Best regards,

Anand.