I need to delay the turn on/off operation such that at Vcc rising, turn is is delayed and otherwise turn off is also delayed when Vcc is falling (of course the UVLO is applicable in parallel).
I want to achieve this by connecting a capacitor (of the order of 100nF) between GND and the EN pin, while R1 (between VCC and EN) is of the order of 100kOhm, and another resistor is in parallel to the capacitor (between EN and GND). By this, the standard resistor divider (for this application, separate from the OV resistor divider), just with an additional capacitor.
This can lead to EN having still a voltage applied (due to the charge of the capacitor) which VCC already has fallen below the voltage at EN. The data sheet does not specify this situation.
VCC is 3.3V nominal. Could a voltage of 3.3V at the EN pin, while VCC is 0V, damage the device? In case, would damage be prevented by using an additional resistor between the resistor divider/capacitor and the EN pin, to limit a current that may flow e.g. via protection diode within the device?
