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BQ77915: internal regulator and CHG FET operation.

Radel Design Team
Intellectual 460 points
Part Number: BQ77915

Hi,

We are intending to use BQ77915 for cell balancing and battery monitoring.

The queries regarding the IC are as follows:

1. Is VDIG regulator's output  continuous or pulsed?

2. How can PACK- go to voltage less than VSS? In section 10.1.1.1 of the datasheet it is said that when gate of the CHG FET reaches ground, the PACK- will start to fall below ground. could you please elaborate?

3.What is the function of switch between output of VDIG regulator and VTB in the functional block diagram?

4. We are using 4 cell configuration of 4.2V each. When the battery pack voltage reaches about 14.5V while charging with a current of about 500mA, the CHG FET drive starts to toggle and if we decrease the charging current to about 80-100mA, the toggling stops. What may be the reason behind this?

Thank you

with regards

Yashaswini k

  • 0
    TI__Guru 54715 points
    Hi Yashaswini,
    1. VDIG (AVDD) is continuous when the device is not hibernated.
    2. As an example the bq7791500 has OTC of 45C and OTD of 65C. UV is 2.9V. If a 5 cell battery is discharged to perhaps 15V and has a temperature rise to 50C, it will be in OTC condition. When placed in a 20.5V charger the PACK- will be 5.5V below battery- and VSS (PACK- = 15 - 20.5 = -5.5). Once the battery cools the OTC will clear and the charge FET will turn on clamping PACK- to battery-. More like the description, if the battery heated to above the OTC trip while charging, CHG would go low turning off the charge FET and allowing PACK- to go below VSS.
    3. The temperature measurement is pulsed to reduce current from the cells to bias the thermistor. The switch is closed only to measure temperature. The data sheet does not describe the timing, but you can observe it with an oscilloscope.
    4. One common situation of a FET toggling is body diode protection, but in this case the behavior is the wrong polarity and the wrong FET for a charge condition.
    A possibility might be an OTC, but the hysteresis should be 10 deg C, it is unlikely the thermistor could cool quickly. At low current there would be less heat generation.
    Another possibility may be a OV condition sensed by the part. At 14.5 V, 4 well matched cells should be well away from the OV limit, but check for unexpected resistance in the connection between cells which may be adding the the apparent cell voltage observed by the IC. When the FET turns off the current stops and the voltage contribution from resistance is gone immediately, so the fault recovers and the FET turns on again. At lower current the resistance would not contribute as much voltage. Check the cell voltages at the board during charge.

    If this does not help, please reply with more description of the behavior and waveforms if possible.
  • 0 in reply to WM5295
    Intellectual 460 points
    Hi,

    Thank you for your response.

    In section 9.3.1 (page no. 15), it is said that the comparator 1 checks for OTC, OTD, UTC, UTD. In the section 9.2 functional block diagram the TS pin is connected to comparator 2. How will the comparator 1 checks the OTC, OTD, UTC, UTD ?

    Regards,
    Yashaswini
  • 0 in reply to Radel Design Team
    TI__Guru 54715 points
    Hi Yashaswini,
    That sentence in section 9.3.1 incorrect, OTC, OTD, UTC, and UTD are checked by comparator 2 as shown in the block diagram. I have input a request to revise the description in a future revision. Thank you for bringing this to our attention.