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TPS549D22: peak current application question

user4782171
Intellectual 1560 points
Part Number: TPS549D22

Hi Team,

   Here have one TPS549D22 peak current application question need your help for it.

   The system load current application would be have two conditions as  follows and need your help to see if it's okay with transient  analysis. 

   Input 12Vdc, output: 0V9 normal

   1. Load Current : Normal load 20A with 1msec period time then to  peak current 100A with 25nsec period time and repeats

   2. Load Current :Normal load 20A with 100usec period time then to peak current 100A with 25nsec period time and repeats

Best regards,

Albert Lee.

  

  • 0
    TI__Guru**** 191445 points

    Albert,

    This will not really affect the converter at all.  25 nsec is too fast, so all the energy will come from the output capacitors.  The pulse width is short enough that the required capacitance is not that much either.  That being said, I don't think your scenario is realistic at all.  No way you can slew to from 20 to 100 A in 25 nsec.  That is a 3200 A/usec slew rate.  I can't see any way you can realistically achieve that.

  • 0 in reply to JohnTucker
    Intellectual 340 points

    Hi John,

    Thanks for your reply. 

    According to capacitance formula Q=CV=It. How many capacitance do we need?

    C x ΔV = ΔI x ttyp => C x 0.05V = (100A-20A) x 25ns => C= 2u / 0.05 = 40uF.

    W=P x t = 1/2CV^2 => C= 2 x P x t / (Vtyp^2 – Vmin^2) => C= 2 x 0.925 x 100A x 25ns / (0.925^2 – 0.875^2) => C= 4.625u / 0.09 = 51.38uF.

    am i right? 

    Cheers,

    Muhsiu.

  • 0 in reply to Muhsiu Wei36
    TI__Guru**** 191445 points

    Muhsiu,

    The real question is your current step.  I find it totally unrealistic.  Can you elaborate?

  • 0 in reply to JohnTucker
    Intellectual 340 points

    Hi John,

    Actually, the instantaneous peak current requirement is from our customer.

    We try to find the correct D2D solution for it.

    Thanks for your remind. I also try to get more detail from customer. 

    Cheers.

    Muhsiu.   

  • 0 in reply to Muhsiu Wei36
    TI__Guru**** 191445 points

    Muhsiu,

    Let me know what you find out.

  • 0 in reply to JohnTucker
    TI__Intellectual 1560 points

    Hi John,

      Just discussed with Muhsiu, the latest current mode would be as following from CPU requirement. Does it can be achieve through TPS549D22 with this transient load? Need your help to have the suggestion and simulation transient load result if it could be? 

       10A (100nsec)-->100A (25nsec)

    Best regards,

    Albert Lee.

      

  • 0 in reply to user4782171
    TI__Guru**** 191445 points

    Albert,

    As I stated earlier, that current step is not realistic.  Any current step of that nature will be supplied directly by the local CPU bypass capacitors.  What CPU is this?  Is the load step repetitive?  What is the rate?

  • 0 in reply to JohnTucker
    TI__Intellectual 1560 points

    Hi John,

       Thanks.  The spec is from customer's end customer. It's a new CPU and the others can't provide at this moment.

       From your information that could be used capacitors to achieve it.for this kind of current. 

       We plan place total 100uF decoupling capacitors on the bottom side of CPU but we can't make sure if it's okay.

       Please help to evaluate how many capacitors should be placed at the D2D output side.

       If TPS549D22 can handle this operating condition? If not, do you have any suggestion for this one?

             

      Additonal spec as follows:

    • Ripple spec: +/-3% of 0.925V
    • DC tolerance :0.925V +/-5%
    • AC tolerance : 0.925V +/-8%
    • 10~100A Slew rate for this spike current as attached: Please help to simulate 5ns/10ns for both rise time and fall time.

    Best regards,

    Albert Lee.

    10A to 100A load.docx

  • 0 in reply to user4782171
    TI__Guru**** 191445 points

    Albert,

    I don't know what they are thinking.  For the sake of argument, let's assume 1 nH ESL.  Then the voltage drop during the transient is 9 V.  The actual parasitics are very likely much worse.  if you add in the ESR effect, that is another 0.3 V drop.  I don't believe the laws of physics will support that.  In the perfect ideal world it could work, but with real world components I doubt it.  The TPS549D22 will not even se those transients,  I t will look like a steady state 28 A load as far as the converter is concerned.  Can you provide details of the customer decoupling scheme?  What type of decoupling capacitors do they plan to use?  Maybe some ultra low ESL types can support it.

  • 0 in reply to JohnTucker
    Intellectual 340 points

    Hi John,

    I understand your concerns. You want to clarify the question as possible before make the decision. In the previous version customer using Intel 60A powerSoC for this power rail design.

    Based on your reply, the converter may only output steady state 28A load. It looks TPS549D22 can handle this.   

    Please check the scheme as illustration.  

    Thanks.

    Muhsiu.

  • 0 in reply to Muhsiu Wei36
    TI__Guru**** 191445 points

    Muhsiu,

    Yes that current stepping will be transparent to the TPS549D22.  The transients will all be coming from the capacitor bank.  It will be an interesting design problem for your customer.  They will need to pay very close attention to the PCB layout to minimize the parasitics.  I still very much doubt that specification though.